Lines Matching refs:cbcr

217 define void @addCombineToVPADD_i8(<16 x i8> *%cbcr, <8 x i8> *%X) nounwind ssp {
224   %tmp = load <16 x i8>, <16 x i8>* %cbcr
234 define void @addCombineToVPADD_i16(<8 x i16> *%cbcr, <4 x i16> *%X) nounwind ssp {
241   %tmp = load <8 x i16>, <8 x i16>* %cbcr
250 define void @addCombineToVPADD_i32(<4 x i32> *%cbcr, <2 x i32> *%X) nounwind ssp {
257   %tmp = load <4 x i32>, <4 x i32>* %cbcr
266 define void @addCombineToVPADDLq_s8(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ssp {
273   %tmp = load <16 x i8>, <16 x i8>* %cbcr
285 define void @addCombineToVPADDL_s8(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp {
296   %tmp = load <16 x i8>, <16 x i8>* %cbcr
307 define void @addCombineToVPADDLq_u8(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ssp {
314   %tmp = load <16 x i8>, <16 x i8>* %cbcr
326 define void @addCombineToVPADDLq_u8_early_zext(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ssp {
336   %tmp = load <16 x i8>, <16 x i8>* %cbcr
347 define void @addCombineToVPADDL_u8(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp {
357   %tmp = load <16 x i8>, <16 x i8>* %cbcr
368 define void @addCombineToVPADDL_u8_early_zext(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp {
376   %tmp = load <16 x i8>, <16 x i8>* %cbcr
386 define void @addCombineToVPADDLq_s16(<8 x i16> *%cbcr, <4 x i32> *%X) nounwind ssp {
393   %tmp = load <8 x i16>, <8 x i16>* %cbcr
404 define void @addCombineToVPADDLq_u16(<8 x i16> *%cbcr, <4 x i32> *%X) nounwind ssp {
411   %tmp = load <8 x i16>, <8 x i16>* %cbcr
422 define void @addCombineToVPADDLq_s32(<4 x i32> *%cbcr, <2 x i64> *%X) nounwind ssp {
429   %tmp = load <4 x i32>, <4 x i32>* %cbcr
440 define void @addCombineToVPADDLq_u32(<4 x i32> *%cbcr, <2 x i64> *%X) nounwind ssp {
447   %tmp = load <4 x i32>, <4 x i32>* %cbcr