Lines Matching refs:SF
9 ; RUN: FileCheck %s -check-prefixes=M32R2-SF
29 ; RUN: FileCheck %s -check-prefixes=MMR2-SF
33 ; RUN: FileCheck %s -check-prefixes=MMR6-SF
61 ; M32R2-SF-LABEL: test1:
62 ; M32R2-SF: # %bb.0: # %entry
63 ; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
64 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
65 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
66 ; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
67 ; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
68 ; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
69 ; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} SW
70 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
71 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
72 ; M32R2-SF-NEXT: # <MCOperand Imm:20>>
73 ; M32R2-SF-NEXT: .cfi_offset 31, -4
74 ; M32R2-SF-NEXT: jal __fixsfsi # <MCInst #{{[0-9]+}} JAL
75 ; M32R2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
76 ; M32R2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
77 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
78 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
79 ; M32R2-SF-NEXT: # <MCOperand Imm:0>>
80 ; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
81 ; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} LW
82 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
83 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
84 ; M32R2-SF-NEXT: # <MCOperand Imm:20>>
85 ; M32R2-SF-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
86 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
87 ; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
88 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
89 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
90 ; M32R2-SF-NEXT: # <MCOperand Imm:24>>
160 ; MMR2-SF-LABEL: test1:
161 ; MMR2-SF: # %bb.0: # %entry
162 ; MMR2-SF-NEXT: addiusp -24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
163 ; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
164 ; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
165 ; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
166 ; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} SWSP_MM
167 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
168 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
169 ; MMR2-SF-NEXT: # <MCOperand Imm:20>>
170 ; MMR2-SF-NEXT: .cfi_offset 31, -4
171 ; MMR2-SF-NEXT: jal __fixsfsi # <MCInst #{{[0-9]+}} JAL_MM
172 ; MMR2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
173 ; MMR2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
174 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
175 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
176 ; MMR2-SF-NEXT: # <MCOperand Imm:0>>
177 ; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
178 ; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} LWSP_MM
179 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
180 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
181 ; MMR2-SF-NEXT: # <MCOperand Imm:20>>
182 ; MMR2-SF-NEXT: addiusp 24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
183 ; MMR2-SF-NEXT: # <MCOperand Imm:24>>
184 ; MMR2-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
185 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
198 ; MMR6-SF-LABEL: test1:
199 ; MMR6-SF: # %bb.0: # %entry
200 ; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
201 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
202 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
203 ; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
204 ; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
205 ; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
206 ; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} SW
207 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
208 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
209 ; MMR6-SF-NEXT: # <MCOperand Imm:20>>
210 ; MMR6-SF-NEXT: .cfi_offset 31, -4
211 ; MMR6-SF-NEXT: balc __fixsfsi # <MCInst #{{[0-9]+}} BALC_MMR6
212 ; MMR6-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
213 ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
214 ; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW
215 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
216 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
217 ; MMR6-SF-NEXT: # <MCOperand Imm:20>>
218 ; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
219 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
220 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
221 ; MMR6-SF-NEXT: # <MCOperand Imm:24>>
222 ; MMR6-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
223 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
252 ; M32R2-SF-LABEL: test2:
253 ; M32R2-SF: # %bb.0: # %entry
254 ; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
255 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
256 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
257 ; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
258 ; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
259 ; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
260 ; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} SW
261 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
262 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
263 ; M32R2-SF-NEXT: # <MCOperand Imm:20>>
264 ; M32R2-SF-NEXT: .cfi_offset 31, -4
265 ; M32R2-SF-NEXT: jal __fixdfsi # <MCInst #{{[0-9]+}} JAL
266 ; M32R2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
267 ; M32R2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
268 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
269 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
270 ; M32R2-SF-NEXT: # <MCOperand Imm:0>>
271 ; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
272 ; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} LW
273 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
274 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
275 ; M32R2-SF-NEXT: # <MCOperand Imm:20>>
276 ; M32R2-SF-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
277 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
278 ; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
279 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
280 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
281 ; M32R2-SF-NEXT: # <MCOperand Imm:24>>
351 ; MMR2-SF-LABEL: test2:
352 ; MMR2-SF: # %bb.0: # %entry
353 ; MMR2-SF-NEXT: addiusp -24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
354 ; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
355 ; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
356 ; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
357 ; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} SWSP_MM
358 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
359 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
360 ; MMR2-SF-NEXT: # <MCOperand Imm:20>>
361 ; MMR2-SF-NEXT: .cfi_offset 31, -4
362 ; MMR2-SF-NEXT: jal __fixdfsi # <MCInst #{{[0-9]+}} JAL_MM
363 ; MMR2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
364 ; MMR2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
365 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
366 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
367 ; MMR2-SF-NEXT: # <MCOperand Imm:0>>
368 ; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
369 ; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} LWSP_MM
370 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
371 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
372 ; MMR2-SF-NEXT: # <MCOperand Imm:20>>
373 ; MMR2-SF-NEXT: addiusp 24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
374 ; MMR2-SF-NEXT: # <MCOperand Imm:24>>
375 ; MMR2-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
376 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
389 ; MMR6-SF-LABEL: test2:
390 ; MMR6-SF: # %bb.0: # %entry
391 ; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
392 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
393 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
394 ; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
395 ; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
396 ; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
397 ; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} SW
398 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
399 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
400 ; MMR6-SF-NEXT: # <MCOperand Imm:20>>
401 ; MMR6-SF-NEXT: .cfi_offset 31, -4
402 ; MMR6-SF-NEXT: balc __fixdfsi # <MCInst #{{[0-9]+}} BALC_MMR6
403 ; MMR6-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
404 ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
405 ; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW
406 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
407 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
408 ; MMR6-SF-NEXT: # <MCOperand Imm:20>>
409 ; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
410 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
411 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
412 ; MMR6-SF-NEXT: # <MCOperand Imm:24>>
413 ; MMR6-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
414 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>