Lines Matching refs:MIPS64
7 …-mtriple=mips64-mti-linux-gnu -mcpu=mips64 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64
95 ; MIPS64-LABEL: f1:
96 ; MIPS64: # %bb.0: # %entry
97 ; MIPS64-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
98 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
99 ; MIPS64-NEXT: # <MCOperand Expr:(%highest(a))>>
100 ; MIPS64-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
101 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
102 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
103 ; MIPS64-NEXT: # <MCOperand Expr:(%higher(a))>>
104 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
105 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
106 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
107 ; MIPS64-NEXT: # <MCOperand Imm:16>>
108 ; MIPS64-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
109 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
110 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
111 ; MIPS64-NEXT: # <MCOperand Expr:(%hi(a))>>
112 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
113 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
114 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
115 ; MIPS64-NEXT: # <MCOperand Imm:16>>
116 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
117 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
118 ; MIPS64-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
119 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
120 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
121 ; MIPS64-NEXT: # <MCOperand Expr:(%lo(a))>>
234 ; MIPS64-LABEL: f2:
235 ; MIPS64: # %bb.0: # %entry
236 ; MIPS64-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
237 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
238 ; MIPS64-NEXT: # <MCOperand Expr:(%highest(a))>>
239 ; MIPS64-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
240 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
241 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
242 ; MIPS64-NEXT: # <MCOperand Expr:(%higher(a))>>
243 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
244 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
245 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
246 ; MIPS64-NEXT: # <MCOperand Imm:16>>
247 ; MIPS64-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
248 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
249 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
250 ; MIPS64-NEXT: # <MCOperand Expr:(%hi(a))>>
251 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
252 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
253 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
254 ; MIPS64-NEXT: # <MCOperand Imm:16>>
255 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
256 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
257 ; MIPS64-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
258 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
259 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
260 ; MIPS64-NEXT: # <MCOperand Expr:(%lo(a))>>
374 ; MIPS64-LABEL: f3:
375 ; MIPS64: # %bb.0: # %entry
376 ; MIPS64-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
377 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
378 ; MIPS64-NEXT: # <MCOperand Expr:(%highest(b))>>
379 ; MIPS64-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
380 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
381 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
382 ; MIPS64-NEXT: # <MCOperand Expr:(%higher(b))>>
383 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
384 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
385 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
386 ; MIPS64-NEXT: # <MCOperand Imm:16>>
387 ; MIPS64-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
388 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
389 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
390 ; MIPS64-NEXT: # <MCOperand Expr:(%hi(b))>>
391 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
392 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
393 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
394 ; MIPS64-NEXT: # <MCOperand Imm:16>>
395 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
396 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
397 ; MIPS64-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
398 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
399 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
400 ; MIPS64-NEXT: # <MCOperand Expr:(%lo(b))>>
513 ; MIPS64-LABEL: f4:
514 ; MIPS64: # %bb.0: # %entry
515 ; MIPS64-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
516 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
517 ; MIPS64-NEXT: # <MCOperand Expr:(%highest(b))>>
518 ; MIPS64-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
519 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
520 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
521 ; MIPS64-NEXT: # <MCOperand Expr:(%higher(b))>>
522 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
523 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
524 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
525 ; MIPS64-NEXT: # <MCOperand Imm:16>>
526 ; MIPS64-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
527 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
528 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
529 ; MIPS64-NEXT: # <MCOperand Expr:(%hi(b))>>
530 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
531 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
532 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
533 ; MIPS64-NEXT: # <MCOperand Imm:16>>
534 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
535 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
536 ; MIPS64-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
537 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
538 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
539 ; MIPS64-NEXT: # <MCOperand Expr:(%lo(b))>>
653 ; MIPS64-LABEL: f5:
654 ; MIPS64: # %bb.0: # %entry
655 ; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
656 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
657 ; MIPS64-NEXT: # <MCOperand Expr:(%highest(c))>>
658 ; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
659 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
660 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
661 ; MIPS64-NEXT: # <MCOperand Expr:(%higher(c))>>
662 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
663 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
664 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
665 ; MIPS64-NEXT: # <MCOperand Imm:16>>
666 ; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
667 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
668 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
669 ; MIPS64-NEXT: # <MCOperand Expr:(%hi(c))>>
670 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
671 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
672 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
673 ; MIPS64-NEXT: # <MCOperand Imm:16>>
674 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
675 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
676 ; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
677 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
678 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
679 ; MIPS64-NEXT: # <MCOperand Expr:(%lo(c))>>
806 ; MIPS64-LABEL: f6:
807 ; MIPS64: # %bb.0: # %entry
808 ; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
809 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
810 ; MIPS64-NEXT: # <MCOperand Expr:(%highest(c))>>
811 ; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
812 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
813 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
814 ; MIPS64-NEXT: # <MCOperand Expr:(%higher(c))>>
815 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
816 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
817 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
818 ; MIPS64-NEXT: # <MCOperand Imm:16>>
819 ; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
820 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
821 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
822 ; MIPS64-NEXT: # <MCOperand Expr:(%hi(c))>>
823 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
824 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
825 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
826 ; MIPS64-NEXT: # <MCOperand Imm:16>>
827 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
828 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
829 ; MIPS64-NEXT: lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
830 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
831 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
832 ; MIPS64-NEXT: # <MCOperand Expr:(%lo(c))>>
962 ; MIPS64-LABEL: f7:
963 ; MIPS64: # %bb.0: # %entry
964 ; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
965 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
966 ; MIPS64-NEXT: # <MCOperand Expr:(%highest(c))>>
967 ; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
968 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
969 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
970 ; MIPS64-NEXT: # <MCOperand Expr:(%higher(c))>>
971 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
972 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
973 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
974 ; MIPS64-NEXT: # <MCOperand Imm:16>>
975 ; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
976 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
977 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
978 ; MIPS64-NEXT: # <MCOperand Expr:(%hi(c))>>
979 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
980 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
981 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
982 ; MIPS64-NEXT: # <MCOperand Imm:16>>
983 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
984 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
985 ; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
986 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
987 ; MIPS64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
988 ; MIPS64-NEXT: # <MCOperand Expr:(%lo(c))>>