Lines Matching refs:flw
217 ; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0)
219 ; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0)
223 ; CHECK-RV32IF-NEXT: flw ft1, 4(sp)
224 ; CHECK-RV32IF-NEXT: flw ft0, 8(sp)
236 ; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0)
238 ; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0)
316 ; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0)
318 ; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0)
322 ; CHECK-RV32IF-NEXT: flw ft1, 12(sp)
323 ; CHECK-RV32IF-NEXT: flw ft0, 16(sp)
340 ; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0)
342 ; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0)
474 ; CHECK-RV32IF-NEXT: flw fs11, 0(sp)
475 ; CHECK-RV32IF-NEXT: flw fs10, 4(sp)
476 ; CHECK-RV32IF-NEXT: flw fs9, 8(sp)
477 ; CHECK-RV32IF-NEXT: flw fs8, 12(sp)
478 ; CHECK-RV32IF-NEXT: flw fs7, 16(sp)
479 ; CHECK-RV32IF-NEXT: flw fs6, 20(sp)
480 ; CHECK-RV32IF-NEXT: flw fs5, 24(sp)
481 ; CHECK-RV32IF-NEXT: flw fs4, 28(sp)
482 ; CHECK-RV32IF-NEXT: flw fs3, 32(sp)
483 ; CHECK-RV32IF-NEXT: flw fs2, 36(sp)
484 ; CHECK-RV32IF-NEXT: flw fs1, 40(sp)
485 ; CHECK-RV32IF-NEXT: flw fs0, 44(sp)
486 ; CHECK-RV32IF-NEXT: flw ft11, 48(sp)
487 ; CHECK-RV32IF-NEXT: flw ft10, 52(sp)
488 ; CHECK-RV32IF-NEXT: flw ft9, 56(sp)
489 ; CHECK-RV32IF-NEXT: flw ft8, 60(sp)
490 ; CHECK-RV32IF-NEXT: flw fa7, 64(sp)
491 ; CHECK-RV32IF-NEXT: flw fa6, 68(sp)
492 ; CHECK-RV32IF-NEXT: flw fa5, 72(sp)
493 ; CHECK-RV32IF-NEXT: flw fa4, 76(sp)
494 ; CHECK-RV32IF-NEXT: flw fa3, 80(sp)
495 ; CHECK-RV32IF-NEXT: flw fa2, 84(sp)
496 ; CHECK-RV32IF-NEXT: flw fa1, 88(sp)
497 ; CHECK-RV32IF-NEXT: flw fa0, 92(sp)
498 ; CHECK-RV32IF-NEXT: flw ft7, 96(sp)
499 ; CHECK-RV32IF-NEXT: flw ft6, 100(sp)
500 ; CHECK-RV32IF-NEXT: flw ft5, 104(sp)
501 ; CHECK-RV32IF-NEXT: flw ft4, 108(sp)
502 ; CHECK-RV32IF-NEXT: flw ft3, 112(sp)
503 ; CHECK-RV32IF-NEXT: flw ft2, 116(sp)
504 ; CHECK-RV32IF-NEXT: flw ft1, 120(sp)
505 ; CHECK-RV32IF-NEXT: flw ft0, 124(sp)
668 ; CHECK-RV32IF-NEXT: flw fs11, 12(sp)
669 ; CHECK-RV32IF-NEXT: flw fs10, 16(sp)
670 ; CHECK-RV32IF-NEXT: flw fs9, 20(sp)
671 ; CHECK-RV32IF-NEXT: flw fs8, 24(sp)
672 ; CHECK-RV32IF-NEXT: flw fs7, 28(sp)
673 ; CHECK-RV32IF-NEXT: flw fs6, 32(sp)
674 ; CHECK-RV32IF-NEXT: flw fs5, 36(sp)
675 ; CHECK-RV32IF-NEXT: flw fs4, 40(sp)
676 ; CHECK-RV32IF-NEXT: flw fs3, 44(sp)
677 ; CHECK-RV32IF-NEXT: flw fs2, 48(sp)
678 ; CHECK-RV32IF-NEXT: flw fs1, 52(sp)
679 ; CHECK-RV32IF-NEXT: flw fs0, 56(sp)
680 ; CHECK-RV32IF-NEXT: flw ft11, 60(sp)
681 ; CHECK-RV32IF-NEXT: flw ft10, 64(sp)
682 ; CHECK-RV32IF-NEXT: flw ft9, 68(sp)
683 ; CHECK-RV32IF-NEXT: flw ft8, 72(sp)
684 ; CHECK-RV32IF-NEXT: flw fa7, 76(sp)
685 ; CHECK-RV32IF-NEXT: flw fa6, 80(sp)
686 ; CHECK-RV32IF-NEXT: flw fa5, 84(sp)
687 ; CHECK-RV32IF-NEXT: flw fa4, 88(sp)
688 ; CHECK-RV32IF-NEXT: flw fa3, 92(sp)
689 ; CHECK-RV32IF-NEXT: flw fa2, 96(sp)
690 ; CHECK-RV32IF-NEXT: flw fa1, 100(sp)
691 ; CHECK-RV32IF-NEXT: flw fa0, 104(sp)
692 ; CHECK-RV32IF-NEXT: flw ft7, 108(sp)
693 ; CHECK-RV32IF-NEXT: flw ft6, 112(sp)
694 ; CHECK-RV32IF-NEXT: flw ft5, 116(sp)
695 ; CHECK-RV32IF-NEXT: flw ft4, 120(sp)
696 ; CHECK-RV32IF-NEXT: flw ft3, 124(sp)
697 ; CHECK-RV32IF-NEXT: flw ft2, 128(sp)
698 ; CHECK-RV32IF-NEXT: flw ft1, 132(sp)
699 ; CHECK-RV32IF-NEXT: flw ft0, 136(sp)