Lines Matching refs:lw
32 ; CHECK-RV32-NEXT: lw a0, %lo(a)(a0)
34 ; CHECK-RV32-NEXT: lw a1, %lo(b)(a1)
38 ; CHECK-RV32-NEXT: lw a1, 8(sp)
39 ; CHECK-RV32-NEXT: lw a0, 12(sp)
49 ; CHECK-RV32IF-NEXT: lw a0, %lo(a)(a0)
51 ; CHECK-RV32IF-NEXT: lw a1, %lo(b)(a1)
55 ; CHECK-RV32IF-NEXT: lw a1, 8(sp)
56 ; CHECK-RV32IF-NEXT: lw a0, 12(sp)
66 ; CHECK-RV32IFD-NEXT: lw a0, %lo(a)(a0)
68 ; CHECK-RV32IFD-NEXT: lw a1, %lo(b)(a1)
72 ; CHECK-RV32IFD-NEXT: lw a1, 8(sp)
73 ; CHECK-RV32IFD-NEXT: lw a0, 12(sp)
97 ; CHECK-RV32-NEXT: lw a0, %lo(a)(a0)
99 ; CHECK-RV32-NEXT: lw a1, %lo(b)(a1)
103 ; CHECK-RV32-NEXT: lw a1, 0(sp)
104 ; CHECK-RV32-NEXT: lw a0, 4(sp)
105 ; CHECK-RV32-NEXT: lw s0, 8(sp)
106 ; CHECK-RV32-NEXT: lw ra, 12(sp)
119 ; CHECK-RV32IF-NEXT: lw a0, %lo(a)(a0)
121 ; CHECK-RV32IF-NEXT: lw a1, %lo(b)(a1)
125 ; CHECK-RV32IF-NEXT: lw a1, 0(sp)
126 ; CHECK-RV32IF-NEXT: lw a0, 4(sp)
127 ; CHECK-RV32IF-NEXT: lw s0, 8(sp)
128 ; CHECK-RV32IF-NEXT: lw ra, 12(sp)
141 ; CHECK-RV32IFD-NEXT: lw a0, %lo(a)(a0)
143 ; CHECK-RV32IFD-NEXT: lw a1, %lo(b)(a1)
147 ; CHECK-RV32IFD-NEXT: lw a1, 0(sp)
148 ; CHECK-RV32IFD-NEXT: lw a0, 4(sp)
149 ; CHECK-RV32IFD-NEXT: lw s0, 8(sp)
150 ; CHECK-RV32IFD-NEXT: lw ra, 12(sp)
185 ; CHECK-RV32-NEXT: lw a0, %lo(e)(a0)
187 ; CHECK-RV32-NEXT: lw a1, %lo(f)(a1)
191 ; CHECK-RV32-NEXT: lw t6, 0(sp)
192 ; CHECK-RV32-NEXT: lw t5, 4(sp)
193 ; CHECK-RV32-NEXT: lw t4, 8(sp)
194 ; CHECK-RV32-NEXT: lw t3, 12(sp)
195 ; CHECK-RV32-NEXT: lw a7, 16(sp)
196 ; CHECK-RV32-NEXT: lw a6, 20(sp)
197 ; CHECK-RV32-NEXT: lw a5, 24(sp)
198 ; CHECK-RV32-NEXT: lw a4, 28(sp)
199 ; CHECK-RV32-NEXT: lw a3, 32(sp)
200 ; CHECK-RV32-NEXT: lw a2, 36(sp)
201 ; CHECK-RV32-NEXT: lw a1, 40(sp)
202 ; CHECK-RV32-NEXT: lw a0, 44(sp)
203 ; CHECK-RV32-NEXT: lw t2, 48(sp)
204 ; CHECK-RV32-NEXT: lw t1, 52(sp)
205 ; CHECK-RV32-NEXT: lw t0, 56(sp)
206 ; CHECK-RV32-NEXT: lw ra, 60(sp)
225 ; CHECK-RV32IF-NEXT: lw a0, 12(sp)
244 ; CHECK-RV32IFD-NEXT: lw a0, 28(sp)
280 ; CHECK-RV32-NEXT: lw a0, %lo(e)(a0)
282 ; CHECK-RV32-NEXT: lw a1, %lo(f)(a1)
286 ; CHECK-RV32-NEXT: lw t6, 12(sp)
287 ; CHECK-RV32-NEXT: lw t5, 16(sp)
288 ; CHECK-RV32-NEXT: lw t4, 20(sp)
289 ; CHECK-RV32-NEXT: lw t3, 24(sp)
290 ; CHECK-RV32-NEXT: lw a7, 28(sp)
291 ; CHECK-RV32-NEXT: lw a6, 32(sp)
292 ; CHECK-RV32-NEXT: lw a5, 36(sp)
293 ; CHECK-RV32-NEXT: lw a4, 40(sp)
294 ; CHECK-RV32-NEXT: lw a3, 44(sp)
295 ; CHECK-RV32-NEXT: lw a2, 48(sp)
296 ; CHECK-RV32-NEXT: lw a1, 52(sp)
297 ; CHECK-RV32-NEXT: lw a0, 56(sp)
298 ; CHECK-RV32-NEXT: lw s0, 60(sp)
299 ; CHECK-RV32-NEXT: lw t2, 64(sp)
300 ; CHECK-RV32-NEXT: lw t1, 68(sp)
301 ; CHECK-RV32-NEXT: lw t0, 72(sp)
302 ; CHECK-RV32-NEXT: lw ra, 76(sp)
324 ; CHECK-RV32IF-NEXT: lw a0, 20(sp)
325 ; CHECK-RV32IF-NEXT: lw s0, 24(sp)
326 ; CHECK-RV32IF-NEXT: lw ra, 28(sp)
348 ; CHECK-RV32IFD-NEXT: lw a0, 20(sp)
349 ; CHECK-RV32IFD-NEXT: lw s0, 24(sp)
350 ; CHECK-RV32IFD-NEXT: lw ra, 28(sp)
385 ; CHECK-RV32-NEXT: lw a0, %lo(h)(a1)
386 ; CHECK-RV32-NEXT: lw a1, %lo(h+4)(a1)
388 ; CHECK-RV32-NEXT: lw a2, %lo(i)(a3)
389 ; CHECK-RV32-NEXT: lw a3, %lo(i+4)(a3)
394 ; CHECK-RV32-NEXT: lw t6, 0(sp)
395 ; CHECK-RV32-NEXT: lw t5, 4(sp)
396 ; CHECK-RV32-NEXT: lw t4, 8(sp)
397 ; CHECK-RV32-NEXT: lw t3, 12(sp)
398 ; CHECK-RV32-NEXT: lw a7, 16(sp)
399 ; CHECK-RV32-NEXT: lw a6, 20(sp)
400 ; CHECK-RV32-NEXT: lw a5, 24(sp)
401 ; CHECK-RV32-NEXT: lw a4, 28(sp)
402 ; CHECK-RV32-NEXT: lw a3, 32(sp)
403 ; CHECK-RV32-NEXT: lw a2, 36(sp)
404 ; CHECK-RV32-NEXT: lw a1, 40(sp)
405 ; CHECK-RV32-NEXT: lw a0, 44(sp)
406 ; CHECK-RV32-NEXT: lw t2, 48(sp)
407 ; CHECK-RV32-NEXT: lw t1, 52(sp)
408 ; CHECK-RV32-NEXT: lw t0, 56(sp)
409 ; CHECK-RV32-NEXT: lw ra, 60(sp)
465 ; CHECK-RV32IF-NEXT: lw a0, %lo(h)(a1)
466 ; CHECK-RV32IF-NEXT: lw a1, %lo(h+4)(a1)
468 ; CHECK-RV32IF-NEXT: lw a2, %lo(i)(a3)
469 ; CHECK-RV32IF-NEXT: lw a3, %lo(i+4)(a3)
506 ; CHECK-RV32IF-NEXT: lw t6, 128(sp)
507 ; CHECK-RV32IF-NEXT: lw t5, 132(sp)
508 ; CHECK-RV32IF-NEXT: lw t4, 136(sp)
509 ; CHECK-RV32IF-NEXT: lw t3, 140(sp)
510 ; CHECK-RV32IF-NEXT: lw a7, 144(sp)
511 ; CHECK-RV32IF-NEXT: lw a6, 148(sp)
512 ; CHECK-RV32IF-NEXT: lw a5, 152(sp)
513 ; CHECK-RV32IF-NEXT: lw a4, 156(sp)
514 ; CHECK-RV32IF-NEXT: lw a3, 160(sp)
515 ; CHECK-RV32IF-NEXT: lw a2, 164(sp)
516 ; CHECK-RV32IF-NEXT: lw a1, 168(sp)
517 ; CHECK-RV32IF-NEXT: lw a0, 172(sp)
518 ; CHECK-RV32IF-NEXT: lw t2, 176(sp)
519 ; CHECK-RV32IF-NEXT: lw t1, 180(sp)
520 ; CHECK-RV32IF-NEXT: lw t0, 184(sp)
521 ; CHECK-RV32IF-NEXT: lw ra, 188(sp)
540 ; CHECK-RV32IFD-NEXT: lw a0, 28(sp)
576 ; CHECK-RV32-NEXT: lw a0, %lo(h)(a1)
577 ; CHECK-RV32-NEXT: lw a1, %lo(h+4)(a1)
579 ; CHECK-RV32-NEXT: lw a2, %lo(i)(a3)
580 ; CHECK-RV32-NEXT: lw a3, %lo(i+4)(a3)
585 ; CHECK-RV32-NEXT: lw t6, 12(sp)
586 ; CHECK-RV32-NEXT: lw t5, 16(sp)
587 ; CHECK-RV32-NEXT: lw t4, 20(sp)
588 ; CHECK-RV32-NEXT: lw t3, 24(sp)
589 ; CHECK-RV32-NEXT: lw a7, 28(sp)
590 ; CHECK-RV32-NEXT: lw a6, 32(sp)
591 ; CHECK-RV32-NEXT: lw a5, 36(sp)
592 ; CHECK-RV32-NEXT: lw a4, 40(sp)
593 ; CHECK-RV32-NEXT: lw a3, 44(sp)
594 ; CHECK-RV32-NEXT: lw a2, 48(sp)
595 ; CHECK-RV32-NEXT: lw a1, 52(sp)
596 ; CHECK-RV32-NEXT: lw a0, 56(sp)
597 ; CHECK-RV32-NEXT: lw s0, 60(sp)
598 ; CHECK-RV32-NEXT: lw t2, 64(sp)
599 ; CHECK-RV32-NEXT: lw t1, 68(sp)
600 ; CHECK-RV32-NEXT: lw t0, 72(sp)
601 ; CHECK-RV32-NEXT: lw ra, 76(sp)
659 ; CHECK-RV32IF-NEXT: lw a0, %lo(h)(a1)
660 ; CHECK-RV32IF-NEXT: lw a1, %lo(h+4)(a1)
662 ; CHECK-RV32IF-NEXT: lw a2, %lo(i)(a3)
663 ; CHECK-RV32IF-NEXT: lw a3, %lo(i+4)(a3)
700 ; CHECK-RV32IF-NEXT: lw t6, 140(sp)
701 ; CHECK-RV32IF-NEXT: lw t5, 144(sp)
702 ; CHECK-RV32IF-NEXT: lw t4, 148(sp)
703 ; CHECK-RV32IF-NEXT: lw t3, 152(sp)
704 ; CHECK-RV32IF-NEXT: lw a7, 156(sp)
705 ; CHECK-RV32IF-NEXT: lw a6, 160(sp)
706 ; CHECK-RV32IF-NEXT: lw a5, 164(sp)
707 ; CHECK-RV32IF-NEXT: lw a4, 168(sp)
708 ; CHECK-RV32IF-NEXT: lw a3, 172(sp)
709 ; CHECK-RV32IF-NEXT: lw a2, 176(sp)
710 ; CHECK-RV32IF-NEXT: lw a1, 180(sp)
711 ; CHECK-RV32IF-NEXT: lw a0, 184(sp)
712 ; CHECK-RV32IF-NEXT: lw s0, 188(sp)
713 ; CHECK-RV32IF-NEXT: lw t2, 192(sp)
714 ; CHECK-RV32IF-NEXT: lw t1, 196(sp)
715 ; CHECK-RV32IF-NEXT: lw t0, 200(sp)
716 ; CHECK-RV32IF-NEXT: lw ra, 204(sp)
738 ; CHECK-RV32IFD-NEXT: lw a0, 20(sp)
739 ; CHECK-RV32IFD-NEXT: lw s0, 24(sp)
740 ; CHECK-RV32IFD-NEXT: lw ra, 28(sp)