Lines Matching refs:v16i1

4 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
14 declare <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x…
195   %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
196 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> %inactive,…
237   %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
238 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> %inactive,…
307   %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
308 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> %inactive,…
349   %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
350 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> %inactive,…
419   %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
420 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> undef, <16…
462   %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
463 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> undef, <16…
534   %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
535 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> undef, <16…
577   %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
578 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> undef, <16…
711   %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
712 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16…
754   %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
755 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16…
797   %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
798 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> %inactive,…
839   %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
840 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> %inactive,…