Lines Matching refs:InVec

9 define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {
18 …%shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 …
22 define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {
33 …%shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 …
37 define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {
48 …%shl = shl <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16…
52 define <8 x i32> @test_slld_1(<8 x i32> %InVec) {
61   %shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
65 define <8 x i32> @test_slld_2(<8 x i32> %InVec) {
76   %shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
99 define <8 x i32> @test_slld_3(<8 x i32> %InVec) {
110   %shl = shl <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
114 define <4 x i64> @test_sllq_1(<4 x i64> %InVec) {
123   %shl = shl <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
127 define <4 x i64> @test_sllq_2(<4 x i64> %InVec) {
138   %shl = shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
142 define <4 x i64> @test_sllq_3(<4 x i64> %InVec) {
153   %shl = shl <4 x i64> %InVec, <i64 63, i64 63, i64 63, i64 63>
159 define <16 x i16> @test_sraw_1(<16 x i16> %InVec) {
168 …%shl = ashr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16…
172 define <16 x i16> @test_sraw_2(<16 x i16> %InVec) {
183 …%shl = ashr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16…
187 define <16 x i16> @test_sraw_3(<16 x i16> %InVec) {
198 …%shl = ashr <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i1…
202 define <8 x i32> @test_srad_1(<8 x i32> %InVec) {
211   %shl = ashr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
215 define <8 x i32> @test_srad_2(<8 x i32> %InVec) {
226   %shl = ashr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
230 define <8 x i32> @test_srad_3(<8 x i32> %InVec) {
241   %shl = ashr <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
247 define <16 x i16> @test_srlw_1(<16 x i16> %InVec) {
256 …%shl = lshr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16…
260 define <16 x i16> @test_srlw_2(<16 x i16> %InVec) {
271 …%shl = lshr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16…
275 define <16 x i16> @test_srlw_3(<16 x i16> %InVec) {
286 …%shl = lshr <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i1…
290 define <8 x i32> @test_srld_1(<8 x i32> %InVec) {
299   %shl = lshr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
303 define <8 x i32> @test_srld_2(<8 x i32> %InVec) {
314   %shl = lshr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
318 define <8 x i32> @test_srld_3(<8 x i32> %InVec) {
329   %shl = lshr <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
333 define <4 x i64> @test_srlq_1(<4 x i64> %InVec) {
342   %shl = lshr <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
346 define <4 x i64> @test_srlq_2(<4 x i64> %InVec) {
357   %shl = lshr <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
361 define <4 x i64> @test_srlq_3(<4 x i64> %InVec) {
372   %shl = lshr <4 x i64> %InVec, <i64 63, i64 63, i64 63, i64 63>