Lines Matching refs:mxcsr
170 ; CHECK: $ymm0 = VMULPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
171 $ymm0 = VMULPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
172 ; CHECK: $ymm0 = VMULPDYrr $ymm0, $ymm1, implicit $mxcsr
173 $ymm0 = VMULPDZ256rr $ymm0, $ymm1, implicit $mxcsr
174 ; CHECK: $ymm0 = VMULPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
175 $ymm0 = VMULPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
176 ; CHECK: $ymm0 = VMULPSYrr $ymm0, $ymm1, implicit $mxcsr
177 $ymm0 = VMULPSZ256rr $ymm0, $ymm1, implicit $mxcsr
318 ; CHECK: $ymm0 = VADDPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
319 $ymm0 = VADDPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
320 ; CHECK: $ymm0 = VADDPDYrr $ymm0, $ymm1, implicit $mxcsr
321 $ymm0 = VADDPDZ256rr $ymm0, $ymm1, implicit $mxcsr
322 ; CHECK: $ymm0 = VADDPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
323 $ymm0 = VADDPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
324 ; CHECK: $ymm0 = VADDPSYrr $ymm0, $ymm1, implicit $mxcsr
325 $ymm0 = VADDPSZ256rr $ymm0, $ymm1, implicit $mxcsr
342 ; CHECK: $ymm0 = VDIVPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
343 $ymm0 = VDIVPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
344 ; CHECK: $ymm0 = VDIVPDYrr $ymm0, $ymm1, implicit $mxcsr
345 $ymm0 = VDIVPDZ256rr $ymm0, $ymm1, implicit $mxcsr
346 ; CHECK: $ymm0 = VDIVPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
347 $ymm0 = VDIVPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
348 ; CHECK: $ymm0 = VDIVPSYrr $ymm0, $ymm1, implicit $mxcsr
349 $ymm0 = VDIVPSZ256rr $ymm0, $ymm1, implicit $mxcsr
350 ; CHECK: $ymm0 = VMAXCPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
351 $ymm0 = VMAXCPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
352 ; CHECK: $ymm0 = VMAXCPDYrr $ymm0, $ymm1, implicit $mxcsr
353 $ymm0 = VMAXCPDZ256rr $ymm0, $ymm1, implicit $mxcsr
354 ; CHECK: $ymm0 = VMAXCPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
355 $ymm0 = VMAXCPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
356 ; CHECK: $ymm0 = VMAXCPSYrr $ymm0, $ymm1, implicit $mxcsr
357 $ymm0 = VMAXCPSZ256rr $ymm0, $ymm1, implicit $mxcsr
358 ; CHECK: $ymm0 = VMAXPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
359 $ymm0 = VMAXPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
360 ; CHECK: $ymm0 = VMAXPDYrr $ymm0, $ymm1, implicit $mxcsr
361 $ymm0 = VMAXPDZ256rr $ymm0, $ymm1, implicit $mxcsr
362 ; CHECK: $ymm0 = VMAXPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
363 $ymm0 = VMAXPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
364 ; CHECK: $ymm0 = VMAXPSYrr $ymm0, $ymm1, implicit $mxcsr
365 $ymm0 = VMAXPSZ256rr $ymm0, $ymm1, implicit $mxcsr
366 ; CHECK: $ymm0 = VMINCPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
367 $ymm0 = VMINCPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
368 ; CHECK: $ymm0 = VMINCPDYrr $ymm0, $ymm1, implicit $mxcsr
369 $ymm0 = VMINCPDZ256rr $ymm0, $ymm1, implicit $mxcsr
370 ; CHECK: $ymm0 = VMINCPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
371 $ymm0 = VMINCPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
372 ; CHECK: $ymm0 = VMINCPSYrr $ymm0, $ymm1, implicit $mxcsr
373 $ymm0 = VMINCPSZ256rr $ymm0, $ymm1, implicit $mxcsr
374 ; CHECK: $ymm0 = VMINPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
375 $ymm0 = VMINPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
376 ; CHECK: $ymm0 = VMINPDYrr $ymm0, $ymm1, implicit $mxcsr
377 $ymm0 = VMINPDZ256rr $ymm0, $ymm1, implicit $mxcsr
378 ; CHECK: $ymm0 = VMINPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
379 $ymm0 = VMINPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
380 ; CHECK: $ymm0 = VMINPSYrr $ymm0, $ymm1, implicit $mxcsr
381 $ymm0 = VMINPSZ256rr $ymm0, $ymm1, implicit $mxcsr
422 ; CHECK: $ymm0 = VSUBPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
423 $ymm0 = VSUBPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
424 ; CHECK: $ymm0 = VSUBPDYrr $ymm0, $ymm1, implicit $mxcsr
425 $ymm0 = VSUBPDZ256rr $ymm0, $ymm1, implicit $mxcsr
426 ; CHECK: $ymm0 = VSUBPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
427 $ymm0 = VSUBPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
428 ; CHECK: $ymm0 = VSUBPSYrr $ymm0, $ymm1, implicit $mxcsr
429 $ymm0 = VSUBPSZ256rr $ymm0, $ymm1, implicit $mxcsr
462 …HECK: $ymm0 = VFMADD132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
463 …m0 = VFMADD132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
464 ; CHECK: $ymm0 = VFMADD132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
465 $ymm0 = VFMADD132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
466 …HECK: $ymm0 = VFMADD132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
467 …m0 = VFMADD132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
468 ; CHECK: $ymm0 = VFMADD132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
469 $ymm0 = VFMADD132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
470 …HECK: $ymm0 = VFMADD213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
471 …m0 = VFMADD213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
472 ; CHECK: $ymm0 = VFMADD213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
473 $ymm0 = VFMADD213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
474 …HECK: $ymm0 = VFMADD213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
475 …m0 = VFMADD213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
476 ; CHECK: $ymm0 = VFMADD213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
477 $ymm0 = VFMADD213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
478 …HECK: $ymm0 = VFMADD231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
479 …m0 = VFMADD231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
480 ; CHECK: $ymm0 = VFMADD231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
481 $ymm0 = VFMADD231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
482 …HECK: $ymm0 = VFMADD231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
483 …m0 = VFMADD231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
484 ; CHECK: $ymm0 = VFMADD231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
485 $ymm0 = VFMADD231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
486 …HECK: $ymm0 = VFMADDSUB132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
487 …m0 = VFMADDSUB132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
488 ; CHECK: $ymm0 = VFMADDSUB132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
489 $ymm0 = VFMADDSUB132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
490 …HECK: $ymm0 = VFMADDSUB132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
491 …m0 = VFMADDSUB132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
492 ; CHECK: $ymm0 = VFMADDSUB132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
493 $ymm0 = VFMADDSUB132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
494 …HECK: $ymm0 = VFMADDSUB213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
495 …m0 = VFMADDSUB213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
496 ; CHECK: $ymm0 = VFMADDSUB213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
497 $ymm0 = VFMADDSUB213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
498 …HECK: $ymm0 = VFMADDSUB213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
499 …m0 = VFMADDSUB213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
500 ; CHECK: $ymm0 = VFMADDSUB213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
501 $ymm0 = VFMADDSUB213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
502 …HECK: $ymm0 = VFMADDSUB231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
503 …m0 = VFMADDSUB231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
504 ; CHECK: $ymm0 = VFMADDSUB231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
505 $ymm0 = VFMADDSUB231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
506 …HECK: $ymm0 = VFMADDSUB231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
507 …m0 = VFMADDSUB231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
508 ; CHECK: $ymm0 = VFMADDSUB231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
509 $ymm0 = VFMADDSUB231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
510 …HECK: $ymm0 = VFMSUB132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
511 …m0 = VFMSUB132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
512 ; CHECK: $ymm0 = VFMSUB132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
513 $ymm0 = VFMSUB132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
514 …HECK: $ymm0 = VFMSUB132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
515 …m0 = VFMSUB132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
516 ; CHECK: $ymm0 = VFMSUB132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
517 $ymm0 = VFMSUB132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
518 …HECK: $ymm0 = VFMSUB213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
519 …m0 = VFMSUB213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
520 ; CHECK: $ymm0 = VFMSUB213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
521 $ymm0 = VFMSUB213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
522 …HECK: $ymm0 = VFMSUB213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
523 …m0 = VFMSUB213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
524 ; CHECK: $ymm0 = VFMSUB213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
525 $ymm0 = VFMSUB213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
526 …HECK: $ymm0 = VFMSUB231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
527 …m0 = VFMSUB231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
528 ; CHECK: $ymm0 = VFMSUB231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
529 $ymm0 = VFMSUB231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
530 …HECK: $ymm0 = VFMSUB231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
531 …m0 = VFMSUB231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
532 ; CHECK: $ymm0 = VFMSUB231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
533 $ymm0 = VFMSUB231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
534 …HECK: $ymm0 = VFMSUBADD132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
535 …m0 = VFMSUBADD132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
536 ; CHECK: $ymm0 = VFMSUBADD132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
537 $ymm0 = VFMSUBADD132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
538 …HECK: $ymm0 = VFMSUBADD132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
539 …m0 = VFMSUBADD132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
540 ; CHECK: $ymm0 = VFMSUBADD132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
541 $ymm0 = VFMSUBADD132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
542 …HECK: $ymm0 = VFMSUBADD213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
543 …m0 = VFMSUBADD213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
544 ; CHECK: $ymm0 = VFMSUBADD213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
545 $ymm0 = VFMSUBADD213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
546 …HECK: $ymm0 = VFMSUBADD213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
547 …m0 = VFMSUBADD213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
548 ; CHECK: $ymm0 = VFMSUBADD213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
549 $ymm0 = VFMSUBADD213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
550 …HECK: $ymm0 = VFMSUBADD231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
551 …m0 = VFMSUBADD231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
552 ; CHECK: $ymm0 = VFMSUBADD231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
553 $ymm0 = VFMSUBADD231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
554 …HECK: $ymm0 = VFMSUBADD231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
555 …m0 = VFMSUBADD231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
556 ; CHECK: $ymm0 = VFMSUBADD231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
557 $ymm0 = VFMSUBADD231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
558 …HECK: $ymm0 = VFNMADD132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
559 …m0 = VFNMADD132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
560 ; CHECK: $ymm0 = VFNMADD132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
561 $ymm0 = VFNMADD132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
562 …HECK: $ymm0 = VFNMADD132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
563 …m0 = VFNMADD132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
564 ; CHECK: $ymm0 = VFNMADD132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
565 $ymm0 = VFNMADD132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
566 …HECK: $ymm0 = VFNMADD213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
567 …m0 = VFNMADD213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
568 ; CHECK: $ymm0 = VFNMADD213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
569 $ymm0 = VFNMADD213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
570 …HECK: $ymm0 = VFNMADD213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
571 …m0 = VFNMADD213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
572 ; CHECK: $ymm0 = VFNMADD213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
573 $ymm0 = VFNMADD213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
574 …HECK: $ymm0 = VFNMADD231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
575 …m0 = VFNMADD231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
576 ; CHECK: $ymm0 = VFNMADD231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
577 $ymm0 = VFNMADD231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
578 …HECK: $ymm0 = VFNMADD231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
579 …m0 = VFNMADD231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
580 ; CHECK: $ymm0 = VFNMADD231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
581 $ymm0 = VFNMADD231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
582 …HECK: $ymm0 = VFNMSUB132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
583 …m0 = VFNMSUB132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
584 ; CHECK: $ymm0 = VFNMSUB132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
585 $ymm0 = VFNMSUB132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
586 …HECK: $ymm0 = VFNMSUB132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
587 …m0 = VFNMSUB132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
588 ; CHECK: $ymm0 = VFNMSUB132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
589 $ymm0 = VFNMSUB132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
590 …HECK: $ymm0 = VFNMSUB213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
591 …m0 = VFNMSUB213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
592 ; CHECK: $ymm0 = VFNMSUB213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
593 $ymm0 = VFNMSUB213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
594 …HECK: $ymm0 = VFNMSUB213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
595 …m0 = VFNMSUB213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
596 ; CHECK: $ymm0 = VFNMSUB213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
597 $ymm0 = VFNMSUB213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
598 …HECK: $ymm0 = VFNMSUB231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
599 …m0 = VFNMSUB231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
600 ; CHECK: $ymm0 = VFNMSUB231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
601 $ymm0 = VFNMSUB231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
602 …HECK: $ymm0 = VFNMSUB231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
603 …m0 = VFNMSUB231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
604 ; CHECK: $ymm0 = VFNMSUB231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
605 $ymm0 = VFNMSUB231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
814 ; CHECK: $ymm0 = VCVTDQ2PSYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
815 $ymm0 = VCVTDQ2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
816 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
817 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
818 ; CHECK: $xmm0 = VCVTPD2DQYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
819 $xmm0 = VCVTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
820 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
821 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
822 ; CHECK: $xmm0 = VCVTPD2PSYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
823 $xmm0 = VCVTPD2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
825 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
826 ; CHECK: $ymm0 = VCVTPS2DQYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
827 $ymm0 = VCVTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
829 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
830 ; CHECK: $ymm0 = VCVTPS2PDYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
831 $ymm0 = VCVTPS2PDZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
832 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
833 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
834 ; CHECK: VCVTPS2PHYmr $rdi, 1, $noreg, 0, $noreg, $ymm0, 0, implicit $mxcsr
835 VCVTPS2PHZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm0, 0, implicit $mxcsr
836 ; CHECK: $xmm0 = VCVTPS2PHYrr $ymm0, 0, implicit $mxcsr
837 $xmm0 = VCVTPS2PHZ256rr $ymm0, 0, implicit $mxcsr
838 ; CHECK: $ymm0 = VCVTPH2PSYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
839 $ymm0 = VCVTPH2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
840 ; CHECK: $ymm0 = VCVTPH2PSYrr $xmm0, implicit $mxcsr
841 $ymm0 = VCVTPH2PSZ256rr $xmm0, implicit $mxcsr
842 ; CHECK: $xmm0 = VCVTTPD2DQYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
843 $xmm0 = VCVTTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
844 ; CHECK: $xmm0 = VCVTTPD2DQYrr $ymm0, implicit $mxcsr
845 $xmm0 = VCVTTPD2DQZ256rr $ymm0, implicit $mxcsr
846 ; CHECK: $ymm0 = VCVTTPS2DQYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
847 $ymm0 = VCVTTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
848 ; CHECK: $ymm0 = VCVTTPS2DQYrr $ymm0, implicit $mxcsr
849 $ymm0 = VCVTTPS2DQZ256rr $ymm0, implicit $mxcsr
850 ; CHECK: $ymm0 = VSQRTPDYm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
851 $ymm0 = VSQRTPDZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
852 ; CHECK: $ymm0 = VSQRTPDYr $ymm0, implicit $mxcsr
853 $ymm0 = VSQRTPDZ256r $ymm0, implicit $mxcsr
854 ; CHECK: $ymm0 = VSQRTPSYm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
855 $ymm0 = VSQRTPSZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
856 ; CHECK: $ymm0 = VSQRTPSYr $ymm0, implicit $mxcsr
857 $ymm0 = VSQRTPSZ256r $ymm0, implicit $mxcsr
892 ; CHECK: $ymm0 = VROUNDPDYm $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
893 $ymm0 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
894 ; CHECK: $ymm0 = VROUNDPDYr $ymm0, 15, implicit $mxcsr
895 $ymm0 = VRNDSCALEPDZ256rri $ymm0, 15, implicit $mxcsr
896 ; CHECK: $ymm0 = VROUNDPSYm $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
897 $ymm0 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
898 ; CHECK: $ymm0 = VROUNDPSYr $ymm0, 15, implicit $mxcsr
899 $ymm0 = VRNDSCALEPSZ256rri $ymm0, 15, implicit $mxcsr
1078 ; CHECK: $xmm0 = VMAXCPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1079 $xmm0 = VMAXCPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1080 ; CHECK: $xmm0 = VMAXCPDrr $xmm0, $xmm1, implicit $mxcsr
1081 $xmm0 = VMAXCPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1082 ; CHECK: $xmm0 = VMAXCPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1083 $xmm0 = VMAXCPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1084 ; CHECK: $xmm0 = VMAXCPSrr $xmm0, $xmm1, implicit $mxcsr
1085 $xmm0 = VMAXCPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1086 ; CHECK: $xmm0 = VMAXPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1087 $xmm0 = VMAXPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1088 ; CHECK: $xmm0 = VMAXPDrr $xmm0, $xmm1, implicit $mxcsr
1089 $xmm0 = VMAXPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1090 ; CHECK: $xmm0 = VMAXPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1091 $xmm0 = VMAXPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1092 ; CHECK: $xmm0 = VMAXPSrr $xmm0, $xmm1, implicit $mxcsr
1093 $xmm0 = VMAXPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1094 ; CHECK: $xmm0 = VMINCPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1095 $xmm0 = VMINCPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1096 ; CHECK: $xmm0 = VMINCPDrr $xmm0, $xmm1, implicit $mxcsr
1097 $xmm0 = VMINCPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1098 ; CHECK: $xmm0 = VMINCPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1099 $xmm0 = VMINCPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1100 ; CHECK: $xmm0 = VMINCPSrr $xmm0, $xmm1, implicit $mxcsr
1101 $xmm0 = VMINCPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1102 ; CHECK: $xmm0 = VMINPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1103 $xmm0 = VMINPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1104 ; CHECK: $xmm0 = VMINPDrr $xmm0, $xmm1, implicit $mxcsr
1105 $xmm0 = VMINPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1106 ; CHECK: $xmm0 = VMINPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1107 $xmm0 = VMINPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1108 ; CHECK: $xmm0 = VMINPSrr $xmm0, $xmm1, implicit $mxcsr
1109 $xmm0 = VMINPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1110 ; CHECK: $xmm0 = VMULPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1111 $xmm0 = VMULPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1112 ; CHECK: $xmm0 = VMULPDrr $xmm0, $xmm1, implicit $mxcsr
1113 $xmm0 = VMULPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1114 ; CHECK: $xmm0 = VMULPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1115 $xmm0 = VMULPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1116 ; CHECK: $xmm0 = VMULPSrr $xmm0, $xmm1, implicit $mxcsr
1117 $xmm0 = VMULPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1298 ; CHECK: $xmm0 = VADDPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1299 $xmm0 = VADDPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1300 ; CHECK: $xmm0 = VADDPDrr $xmm0, $xmm1, implicit $mxcsr
1301 $xmm0 = VADDPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1302 ; CHECK: $xmm0 = VADDPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1303 $xmm0 = VADDPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1304 ; CHECK: $xmm0 = VADDPSrr $xmm0, $xmm1, implicit $mxcsr
1305 $xmm0 = VADDPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1322 ; CHECK: $xmm0 = VDIVPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1323 $xmm0 = VDIVPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1324 ; CHECK: $xmm0 = VDIVPDrr $xmm0, $xmm1, implicit $mxcsr
1325 $xmm0 = VDIVPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1326 ; CHECK: $xmm0 = VDIVPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1327 $xmm0 = VDIVPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1328 ; CHECK: $xmm0 = VDIVPSrr $xmm0, $xmm1, implicit $mxcsr
1329 $xmm0 = VDIVPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1338 ; CHECK: $xmm0 = VSUBPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1339 $xmm0 = VSUBPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1340 ; CHECK: $xmm0 = VSUBPDrr $xmm0, $xmm1, implicit $mxcsr
1341 $xmm0 = VSUBPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1342 ; CHECK: $xmm0 = VSUBPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1343 $xmm0 = VSUBPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1344 ; CHECK: $xmm0 = VSUBPSrr $xmm0, $xmm1, implicit $mxcsr
1345 $xmm0 = VSUBPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1426 …HECK: $xmm0 = VFMADD132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1427 …m0 = VFMADD132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1428 ; CHECK: $xmm0 = VFMADD132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1429 $xmm0 = VFMADD132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1430 …HECK: $xmm0 = VFMADD132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1431 …m0 = VFMADD132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1432 ; CHECK: $xmm0 = VFMADD132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1433 $xmm0 = VFMADD132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1434 …HECK: $xmm0 = VFMADD213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1435 …m0 = VFMADD213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1436 ; CHECK: $xmm0 = VFMADD213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1437 $xmm0 = VFMADD213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1438 …HECK: $xmm0 = VFMADD213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1439 …m0 = VFMADD213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1440 ; CHECK: $xmm0 = VFMADD213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1441 $xmm0 = VFMADD213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1442 …HECK: $xmm0 = VFMADD231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1443 …m0 = VFMADD231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1444 ; CHECK: $xmm0 = VFMADD231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1445 $xmm0 = VFMADD231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1446 …HECK: $xmm0 = VFMADD231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1447 …m0 = VFMADD231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1448 ; CHECK: $xmm0 = VFMADD231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1449 $xmm0 = VFMADD231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1450 …HECK: $xmm0 = VFMADDSUB132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1451 …m0 = VFMADDSUB132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1452 ; CHECK: $xmm0 = VFMADDSUB132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1453 $xmm0 = VFMADDSUB132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1454 …HECK: $xmm0 = VFMADDSUB132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1455 …m0 = VFMADDSUB132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1456 ; CHECK: $xmm0 = VFMADDSUB132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1457 $xmm0 = VFMADDSUB132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1458 …HECK: $xmm0 = VFMADDSUB213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1459 …m0 = VFMADDSUB213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1460 ; CHECK: $xmm0 = VFMADDSUB213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1461 $xmm0 = VFMADDSUB213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1462 …HECK: $xmm0 = VFMADDSUB213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1463 …m0 = VFMADDSUB213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1464 ; CHECK: $xmm0 = VFMADDSUB213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1465 $xmm0 = VFMADDSUB213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1466 …HECK: $xmm0 = VFMADDSUB231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1467 …m0 = VFMADDSUB231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1468 ; CHECK: $xmm0 = VFMADDSUB231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1469 $xmm0 = VFMADDSUB231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1470 …HECK: $xmm0 = VFMADDSUB231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1471 …m0 = VFMADDSUB231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1472 ; CHECK: $xmm0 = VFMADDSUB231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1473 $xmm0 = VFMADDSUB231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1474 …HECK: $xmm0 = VFMSUB132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1475 …m0 = VFMSUB132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1476 ; CHECK: $xmm0 = VFMSUB132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1477 $xmm0 = VFMSUB132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1478 …HECK: $xmm0 = VFMSUB132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1479 …m0 = VFMSUB132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1480 ; CHECK: $xmm0 = VFMSUB132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1481 $xmm0 = VFMSUB132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1482 …HECK: $xmm0 = VFMSUB213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1483 …m0 = VFMSUB213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1484 ; CHECK: $xmm0 = VFMSUB213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1485 $xmm0 = VFMSUB213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1486 …HECK: $xmm0 = VFMSUB213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1487 …m0 = VFMSUB213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1488 ; CHECK: $xmm0 = VFMSUB213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1489 $xmm0 = VFMSUB213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1490 …HECK: $xmm0 = VFMSUB231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1491 …m0 = VFMSUB231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1492 ; CHECK: $xmm0 = VFMSUB231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1493 $xmm0 = VFMSUB231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1494 …HECK: $xmm0 = VFMSUB231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1495 …m0 = VFMSUB231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1496 ; CHECK: $xmm0 = VFMSUB231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1497 $xmm0 = VFMSUB231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1498 …HECK: $xmm0 = VFMSUBADD132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1499 …m0 = VFMSUBADD132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1500 ; CHECK: $xmm0 = VFMSUBADD132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1501 $xmm0 = VFMSUBADD132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1502 …HECK: $xmm0 = VFMSUBADD132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1503 …m0 = VFMSUBADD132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1504 ; CHECK: $xmm0 = VFMSUBADD132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1505 $xmm0 = VFMSUBADD132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1506 …HECK: $xmm0 = VFMSUBADD213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1507 …m0 = VFMSUBADD213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1508 ; CHECK: $xmm0 = VFMSUBADD213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1509 $xmm0 = VFMSUBADD213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1510 …HECK: $xmm0 = VFMSUBADD213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1511 …m0 = VFMSUBADD213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1512 ; CHECK: $xmm0 = VFMSUBADD213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1513 $xmm0 = VFMSUBADD213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1514 …HECK: $xmm0 = VFMSUBADD231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1515 …m0 = VFMSUBADD231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1516 ; CHECK: $xmm0 = VFMSUBADD231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1517 $xmm0 = VFMSUBADD231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1518 …HECK: $xmm0 = VFMSUBADD231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1519 …m0 = VFMSUBADD231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1520 ; CHECK: $xmm0 = VFMSUBADD231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1521 $xmm0 = VFMSUBADD231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1522 …HECK: $xmm0 = VFNMADD132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1523 …m0 = VFNMADD132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1524 ; CHECK: $xmm0 = VFNMADD132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1525 $xmm0 = VFNMADD132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1526 …HECK: $xmm0 = VFNMADD132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1527 …m0 = VFNMADD132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1528 ; CHECK: $xmm0 = VFNMADD132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1529 $xmm0 = VFNMADD132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1530 …HECK: $xmm0 = VFNMADD213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1531 …m0 = VFNMADD213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1532 ; CHECK: $xmm0 = VFNMADD213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1533 $xmm0 = VFNMADD213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1534 …HECK: $xmm0 = VFNMADD213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1535 …m0 = VFNMADD213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1536 ; CHECK: $xmm0 = VFNMADD213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1537 $xmm0 = VFNMADD213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1538 …HECK: $xmm0 = VFNMADD231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1539 …m0 = VFNMADD231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1540 ; CHECK: $xmm0 = VFNMADD231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1541 $xmm0 = VFNMADD231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1542 …HECK: $xmm0 = VFNMADD231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1543 …m0 = VFNMADD231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1544 ; CHECK: $xmm0 = VFNMADD231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1545 $xmm0 = VFNMADD231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1546 …HECK: $xmm0 = VFNMSUB132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1547 …m0 = VFNMSUB132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1548 ; CHECK: $xmm0 = VFNMSUB132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1549 $xmm0 = VFNMSUB132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1550 …HECK: $xmm0 = VFNMSUB132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1551 …m0 = VFNMSUB132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1552 ; CHECK: $xmm0 = VFNMSUB132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1553 $xmm0 = VFNMSUB132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1554 …HECK: $xmm0 = VFNMSUB213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1555 …m0 = VFNMSUB213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1556 ; CHECK: $xmm0 = VFNMSUB213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1557 $xmm0 = VFNMSUB213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1558 …HECK: $xmm0 = VFNMSUB213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1559 …m0 = VFNMSUB213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1560 ; CHECK: $xmm0 = VFNMSUB213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1561 $xmm0 = VFNMSUB213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1562 …HECK: $xmm0 = VFNMSUB231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1563 …m0 = VFNMSUB231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1564 ; CHECK: $xmm0 = VFNMSUB231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1565 $xmm0 = VFNMSUB231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1566 …HECK: $xmm0 = VFNMSUB231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1567 …m0 = VFNMSUB231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1568 ; CHECK: $xmm0 = VFNMSUB231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1569 $xmm0 = VFNMSUB231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1656 ; CHECK: $xmm0 = VCVTPH2PSrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1657 $xmm0 = VCVTPH2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1658 ; CHECK: $xmm0 = VCVTPH2PSrr $xmm0, implicit $mxcsr
1659 $xmm0 = VCVTPH2PSZ128rr $xmm0, implicit $mxcsr
1664 ; CHECK: $xmm0 = VCVTDQ2PSrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1665 $xmm0 = VCVTDQ2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1666 ; CHECK: $xmm0 = VCVTDQ2PSrr $xmm0, implicit $mxcsr
1667 $xmm0 = VCVTDQ2PSZ128rr $xmm0, implicit $mxcsr
1668 ; CHECK: $xmm0 = VCVTPD2DQrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1669 $xmm0 = VCVTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1670 ; CHECK: $xmm0 = VCVTPD2DQrr $xmm0, implicit $mxcsr
1671 $xmm0 = VCVTPD2DQZ128rr $xmm0, implicit $mxcsr
1672 ; CHECK: $xmm0 = VCVTPD2PSrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1673 $xmm0 = VCVTPD2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1674 ; CHECK: $xmm0 = VCVTPD2PSrr $xmm0, implicit $mxcsr
1675 $xmm0 = VCVTPD2PSZ128rr $xmm0, implicit $mxcsr
1676 ; CHECK: $xmm0 = VCVTPS2DQrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1677 $xmm0 = VCVTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1678 ; CHECK: $xmm0 = VCVTPS2DQrr $xmm0, implicit $mxcsr
1679 $xmm0 = VCVTPS2DQZ128rr $xmm0, implicit $mxcsr
1680 ; CHECK: $xmm0 = VCVTPS2PDrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1681 $xmm0 = VCVTPS2PDZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1682 ; CHECK: $xmm0 = VCVTPS2PDrr $xmm0, implicit $mxcsr
1683 $xmm0 = VCVTPS2PDZ128rr $xmm0, implicit $mxcsr
1684 ; CHECK: $xmm0 = VCVTTPD2DQrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1685 $xmm0 = VCVTTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1686 ; CHECK: $xmm0 = VCVTTPD2DQrr $xmm0, implicit $mxcsr
1687 $xmm0 = VCVTTPD2DQZ128rr $xmm0, implicit $mxcsr
1688 ; CHECK: $xmm0 = VCVTTPS2DQrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1689 $xmm0 = VCVTTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1690 ; CHECK: $xmm0 = VCVTTPS2DQrr $xmm0, implicit $mxcsr
1691 $xmm0 = VCVTTPS2DQZ128rr $xmm0, implicit $mxcsr
1692 ; CHECK: $xmm0 = VSQRTPDm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1693 $xmm0 = VSQRTPDZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1694 ; CHECK: $xmm0 = VSQRTPDr $xmm0, implicit $mxcsr
1695 $xmm0 = VSQRTPDZ128r $xmm0, implicit $mxcsr
1696 ; CHECK: $xmm0 = VSQRTPSm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1697 $xmm0 = VSQRTPSZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1698 ; CHECK: $xmm0 = VSQRTPSr $xmm0, implicit $mxcsr
1699 $xmm0 = VSQRTPSZ128r $xmm0, implicit $mxcsr
1766 ; CHECK: $xmm0 = VCVTPS2PHrr $xmm0, 2, implicit $mxcsr
1767 $xmm0 = VCVTPS2PHZ128rr $xmm0, 2, implicit $mxcsr
1768 ; CHECK: VCVTPS2PHmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 2, implicit $mxcsr
1769 VCVTPS2PHZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0, 2, implicit $mxcsr
1794 ; CHECK: $xmm0 = VROUNDPDm $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
1795 $xmm0 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
1796 ; CHECK: $xmm0 = VROUNDPDr $xmm0, 15, implicit $mxcsr
1797 $xmm0 = VRNDSCALEPDZ128rri $xmm0, 15, implicit $mxcsr
1798 ; CHECK: $xmm0 = VROUNDPSm $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
1799 $xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
1800 ; CHECK: $xmm0 = VROUNDPSr $xmm0, 15, implicit $mxcsr
1801 $xmm0 = VRNDSCALEPSZ128rri $xmm0, 15, implicit $mxcsr
1813 ; CHECK: $xmm0 = VADDSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1814 $xmm0 = VADDSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1815 ; CHECK: $xmm0 = VADDSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1816 $xmm0 = VADDSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1817 ; CHECK: $xmm0 = VADDSDrr $xmm0, $xmm1, implicit $mxcsr
1818 $xmm0 = VADDSDZrr $xmm0, $xmm1, implicit $mxcsr
1819 ; CHECK: $xmm0 = VADDSDrr_Int $xmm0, $xmm1, implicit $mxcsr
1820 $xmm0 = VADDSDZrr_Int $xmm0, $xmm1, implicit $mxcsr
1821 ; CHECK: $xmm0 = VADDSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1822 $xmm0 = VADDSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1823 ; CHECK: $xmm0 = VADDSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1824 $xmm0 = VADDSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1825 ; CHECK: $xmm0 = VADDSSrr $xmm0, $xmm1, implicit $mxcsr
1826 $xmm0 = VADDSSZrr $xmm0, $xmm1, implicit $mxcsr
1827 ; CHECK: $xmm0 = VADDSSrr_Int $xmm0, $xmm1, implicit $mxcsr
1828 $xmm0 = VADDSSZrr_Int $xmm0, $xmm1, implicit $mxcsr
1829 ; CHECK: $xmm0 = VDIVSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1830 $xmm0 = VDIVSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1831 ; CHECK: $xmm0 = VDIVSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1832 $xmm0 = VDIVSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1833 ; CHECK: $xmm0 = VDIVSDrr $xmm0, $xmm1, implicit $mxcsr
1834 $xmm0 = VDIVSDZrr $xmm0, $xmm1, implicit $mxcsr
1835 ; CHECK: $xmm0 = VDIVSDrr_Int $xmm0, $xmm1, implicit $mxcsr
1836 $xmm0 = VDIVSDZrr_Int $xmm0, $xmm1, implicit $mxcsr
1837 ; CHECK: $xmm0 = VDIVSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1838 $xmm0 = VDIVSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1839 ; CHECK: $xmm0 = VDIVSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1840 $xmm0 = VDIVSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1841 ; CHECK: $xmm0 = VDIVSSrr $xmm0, $xmm1, implicit $mxcsr
1842 $xmm0 = VDIVSSZrr $xmm0, $xmm1, implicit $mxcsr
1843 ; CHECK: $xmm0 = VDIVSSrr_Int $xmm0, $xmm1, implicit $mxcsr
1844 $xmm0 = VDIVSSZrr_Int $xmm0, $xmm1, implicit $mxcsr
1845 ; CHECK: $xmm0 = VMAXCSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1846 $xmm0 = VMAXCSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1847 ; CHECK: $xmm0 = VMAXCSDrr $xmm0, $xmm1, implicit $mxcsr
1848 $xmm0 = VMAXCSDZrr $xmm0, $xmm1, implicit $mxcsr
1849 ; CHECK: $xmm0 = VMAXCSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1850 $xmm0 = VMAXCSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1851 ; CHECK: $xmm0 = VMAXCSSrr $xmm0, $xmm1, implicit $mxcsr
1852 $xmm0 = VMAXCSSZrr $xmm0, $xmm1, implicit $mxcsr
1853 ; CHECK: $xmm0 = VMAXSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1854 $xmm0 = VMAXSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1855 ; CHECK: $xmm0 = VMAXSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1856 $xmm0 = VMAXSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1857 ; CHECK: $xmm0 = VMAXSDrr $xmm0, $xmm1, implicit $mxcsr
1858 $xmm0 = VMAXSDZrr $xmm0, $xmm1, implicit $mxcsr
1859 ; CHECK: $xmm0 = VMAXSDrr_Int $xmm0, $xmm1, implicit $mxcsr
1860 $xmm0 = VMAXSDZrr_Int $xmm0, $xmm1, implicit $mxcsr
1861 ; CHECK: $xmm0 = VMAXSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1862 $xmm0 = VMAXSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1863 ; CHECK: $xmm0 = VMAXSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1864 $xmm0 = VMAXSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1865 ; CHECK: $xmm0 = VMAXSSrr $xmm0, $xmm1, implicit $mxcsr
1866 $xmm0 = VMAXSSZrr $xmm0, $xmm1, implicit $mxcsr
1867 ; CHECK: $xmm0 = VMAXSSrr_Int $xmm0, $xmm1, implicit $mxcsr
1868 $xmm0 = VMAXSSZrr_Int $xmm0, $xmm1, implicit $mxcsr
1869 ; CHECK: $xmm0 = VMINCSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1870 $xmm0 = VMINCSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1871 ; CHECK: $xmm0 = VMINCSDrr $xmm0, $xmm1, implicit $mxcsr
1872 $xmm0 = VMINCSDZrr $xmm0, $xmm1, implicit $mxcsr
1873 ; CHECK: $xmm0 = VMINCSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1874 $xmm0 = VMINCSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1875 ; CHECK: $xmm0 = VMINCSSrr $xmm0, $xmm1, implicit $mxcsr
1876 $xmm0 = VMINCSSZrr $xmm0, $xmm1, implicit $mxcsr
1877 ; CHECK: $xmm0 = VMINSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1878 $xmm0 = VMINSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1879 ; CHECK: $xmm0 = VMINSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1880 $xmm0 = VMINSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1881 ; CHECK: $xmm0 = VMINSDrr $xmm0, $xmm1, implicit $mxcsr
1882 $xmm0 = VMINSDZrr $xmm0, $xmm1, implicit $mxcsr
1883 ; CHECK: $xmm0 = VMINSDrr_Int $xmm0, $xmm1, implicit $mxcsr
1884 $xmm0 = VMINSDZrr_Int $xmm0, $xmm1, implicit $mxcsr
1885 ; CHECK: $xmm0 = VMINSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1886 $xmm0 = VMINSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1887 ; CHECK: $xmm0 = VMINSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1888 $xmm0 = VMINSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1889 ; CHECK: $xmm0 = VMINSSrr $xmm0, $xmm1, implicit $mxcsr
1890 $xmm0 = VMINSSZrr $xmm0, $xmm1, implicit $mxcsr
1891 ; CHECK: $xmm0 = VMINSSrr_Int $xmm0, $xmm1, implicit $mxcsr
1892 $xmm0 = VMINSSZrr_Int $xmm0, $xmm1, implicit $mxcsr
1893 ; CHECK: $xmm0 = VMULSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1894 $xmm0 = VMULSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1895 ; CHECK: $xmm0 = VMULSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1896 $xmm0 = VMULSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1897 ; CHECK: $xmm0 = VMULSDrr $xmm0, $xmm1, implicit $mxcsr
1898 $xmm0 = VMULSDZrr $xmm0, $xmm1, implicit $mxcsr
1899 ; CHECK: $xmm0 = VMULSDrr_Int $xmm0, $xmm1, implicit $mxcsr
1900 $xmm0 = VMULSDZrr_Int $xmm0, $xmm1, implicit $mxcsr
1901 ; CHECK: $xmm0 = VMULSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1902 $xmm0 = VMULSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1903 ; CHECK: $xmm0 = VMULSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1904 $xmm0 = VMULSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1905 ; CHECK: $xmm0 = VMULSSrr $xmm0, $xmm1, implicit $mxcsr
1906 $xmm0 = VMULSSZrr $xmm0, $xmm1, implicit $mxcsr
1907 ; CHECK: $xmm0 = VMULSSrr_Int $xmm0, $xmm1, implicit $mxcsr
1908 $xmm0 = VMULSSZrr_Int $xmm0, $xmm1, implicit $mxcsr
1909 ; CHECK: $xmm0 = VSUBSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1910 $xmm0 = VSUBSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1911 ; CHECK: $xmm0 = VSUBSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1912 $xmm0 = VSUBSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1913 ; CHECK: $xmm0 = VSUBSDrr $xmm0, $xmm1, implicit $mxcsr
1914 $xmm0 = VSUBSDZrr $xmm0, $xmm1, implicit $mxcsr
1915 ; CHECK: $xmm0 = VSUBSDrr_Int $xmm0, $xmm1, implicit $mxcsr
1916 $xmm0 = VSUBSDZrr_Int $xmm0, $xmm1, implicit $mxcsr
1917 ; CHECK: $xmm0 = VSUBSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1918 $xmm0 = VSUBSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1919 ; CHECK: $xmm0 = VSUBSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1920 $xmm0 = VSUBSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1921 ; CHECK: $xmm0 = VSUBSSrr $xmm0, $xmm1, implicit $mxcsr
1922 $xmm0 = VSUBSSZrr $xmm0, $xmm1, implicit $mxcsr
1923 ; CHECK: $xmm0 = VSUBSSrr_Int $xmm0, $xmm1, implicit $mxcsr
1924 $xmm0 = VSUBSSZrr_Int $xmm0, $xmm1, implicit $mxcsr
1925 …HECK: $xmm0 = VFMADD132SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1926 …m0 = VFMADD132SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1927 …HECK: $xmm0 = VFMADD132SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1928 …m0 = VFMADD132SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1929 ; CHECK: $xmm0 = VFMADD132SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1930 $xmm0 = VFMADD132SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1931 ; CHECK: $xmm0 = VFMADD132SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1932 $xmm0 = VFMADD132SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1933 …HECK: $xmm0 = VFMADD132SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1934 …m0 = VFMADD132SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1935 …HECK: $xmm0 = VFMADD132SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1936 …m0 = VFMADD132SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1937 ; CHECK: $xmm0 = VFMADD132SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1938 $xmm0 = VFMADD132SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1939 ; CHECK: $xmm0 = VFMADD132SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1940 $xmm0 = VFMADD132SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1941 …HECK: $xmm0 = VFMADD213SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1942 …m0 = VFMADD213SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1943 …HECK: $xmm0 = VFMADD213SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1944 …m0 = VFMADD213SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1945 ; CHECK: $xmm0 = VFMADD213SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1946 $xmm0 = VFMADD213SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1947 ; CHECK: $xmm0 = VFMADD213SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1948 $xmm0 = VFMADD213SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1949 …HECK: $xmm0 = VFMADD213SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1950 …m0 = VFMADD213SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1951 …HECK: $xmm0 = VFMADD213SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1952 …m0 = VFMADD213SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1953 ; CHECK: $xmm0 = VFMADD213SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1954 $xmm0 = VFMADD213SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1955 ; CHECK: $xmm0 = VFMADD213SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1956 $xmm0 = VFMADD213SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1957 …HECK: $xmm0 = VFMADD231SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1958 …m0 = VFMADD231SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1959 …HECK: $xmm0 = VFMADD231SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1960 …m0 = VFMADD231SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1961 ; CHECK: $xmm0 = VFMADD231SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1962 $xmm0 = VFMADD231SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1963 ; CHECK: $xmm0 = VFMADD231SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1964 $xmm0 = VFMADD231SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1965 …HECK: $xmm0 = VFMADD231SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1966 …m0 = VFMADD231SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1967 …HECK: $xmm0 = VFMADD231SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1968 …m0 = VFMADD231SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1969 ; CHECK: $xmm0 = VFMADD231SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1970 $xmm0 = VFMADD231SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1971 ; CHECK: $xmm0 = VFMADD231SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1972 $xmm0 = VFMADD231SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1973 …HECK: $xmm0 = VFMSUB132SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1974 …m0 = VFMSUB132SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1975 …HECK: $xmm0 = VFMSUB132SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1976 …m0 = VFMSUB132SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1977 ; CHECK: $xmm0 = VFMSUB132SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1978 $xmm0 = VFMSUB132SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1979 ; CHECK: $xmm0 = VFMSUB132SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1980 $xmm0 = VFMSUB132SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1981 …HECK: $xmm0 = VFMSUB132SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1982 …m0 = VFMSUB132SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1983 …HECK: $xmm0 = VFMSUB132SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1984 …m0 = VFMSUB132SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1985 ; CHECK: $xmm0 = VFMSUB132SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1986 $xmm0 = VFMSUB132SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1987 ; CHECK: $xmm0 = VFMSUB132SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1988 $xmm0 = VFMSUB132SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1989 …HECK: $xmm0 = VFMSUB213SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1990 …m0 = VFMSUB213SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1991 …HECK: $xmm0 = VFMSUB213SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1992 …m0 = VFMSUB213SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1993 ; CHECK: $xmm0 = VFMSUB213SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1994 $xmm0 = VFMSUB213SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1995 ; CHECK: $xmm0 = VFMSUB213SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1996 $xmm0 = VFMSUB213SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1997 …HECK: $xmm0 = VFMSUB213SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1998 …m0 = VFMSUB213SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1999 …HECK: $xmm0 = VFMSUB213SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2000 …m0 = VFMSUB213SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2001 ; CHECK: $xmm0 = VFMSUB213SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2002 $xmm0 = VFMSUB213SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2003 ; CHECK: $xmm0 = VFMSUB213SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2004 $xmm0 = VFMSUB213SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2005 …HECK: $xmm0 = VFMSUB231SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2006 …m0 = VFMSUB231SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2007 …HECK: $xmm0 = VFMSUB231SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2008 …m0 = VFMSUB231SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2009 ; CHECK: $xmm0 = VFMSUB231SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2010 $xmm0 = VFMSUB231SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2011 ; CHECK: $xmm0 = VFMSUB231SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2012 $xmm0 = VFMSUB231SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2013 …HECK: $xmm0 = VFMSUB231SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2014 …m0 = VFMSUB231SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2015 …HECK: $xmm0 = VFMSUB231SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2016 …m0 = VFMSUB231SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2017 ; CHECK: $xmm0 = VFMSUB231SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2018 $xmm0 = VFMSUB231SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2019 ; CHECK: $xmm0 = VFMSUB231SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2020 $xmm0 = VFMSUB231SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2021 …HECK: $xmm0 = VFNMADD132SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2022 …m0 = VFNMADD132SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2023 …HECK: $xmm0 = VFNMADD132SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2024 …m0 = VFNMADD132SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2025 ; CHECK: $xmm0 = VFNMADD132SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2026 $xmm0 = VFNMADD132SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2027 ; CHECK: $xmm0 = VFNMADD132SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2028 $xmm0 = VFNMADD132SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2029 …HECK: $xmm0 = VFNMADD132SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2030 …m0 = VFNMADD132SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2031 …HECK: $xmm0 = VFNMADD132SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2032 …m0 = VFNMADD132SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2033 ; CHECK: $xmm0 = VFNMADD132SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2034 $xmm0 = VFNMADD132SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2035 ; CHECK: $xmm0 = VFNMADD132SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2036 $xmm0 = VFNMADD132SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2037 …HECK: $xmm0 = VFNMADD213SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2038 …m0 = VFNMADD213SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2039 …HECK: $xmm0 = VFNMADD213SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2040 …m0 = VFNMADD213SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2041 ; CHECK: $xmm0 = VFNMADD213SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2042 $xmm0 = VFNMADD213SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2043 ; CHECK: $xmm0 = VFNMADD213SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2044 $xmm0 = VFNMADD213SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2045 …HECK: $xmm0 = VFNMADD213SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2046 …m0 = VFNMADD213SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2047 …HECK: $xmm0 = VFNMADD213SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2048 …m0 = VFNMADD213SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2049 ; CHECK: $xmm0 = VFNMADD213SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2050 $xmm0 = VFNMADD213SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2051 ; CHECK: $xmm0 = VFNMADD213SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2052 $xmm0 = VFNMADD213SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2053 …HECK: $xmm0 = VFNMADD231SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2054 …m0 = VFNMADD231SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2055 …HECK: $xmm0 = VFNMADD231SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2056 …m0 = VFNMADD231SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2057 ; CHECK: $xmm0 = VFNMADD231SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2058 $xmm0 = VFNMADD231SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2059 ; CHECK: $xmm0 = VFNMADD231SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2060 $xmm0 = VFNMADD231SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2061 …HECK: $xmm0 = VFNMADD231SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2062 …m0 = VFNMADD231SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2063 …HECK: $xmm0 = VFNMADD231SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2064 …m0 = VFNMADD231SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2065 ; CHECK: $xmm0 = VFNMADD231SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2066 $xmm0 = VFNMADD231SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2067 ; CHECK: $xmm0 = VFNMADD231SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2068 $xmm0 = VFNMADD231SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2069 …HECK: $xmm0 = VFNMSUB132SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2070 …m0 = VFNMSUB132SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2071 …HECK: $xmm0 = VFNMSUB132SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2072 …m0 = VFNMSUB132SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2073 ; CHECK: $xmm0 = VFNMSUB132SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2074 $xmm0 = VFNMSUB132SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2075 ; CHECK: $xmm0 = VFNMSUB132SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2076 $xmm0 = VFNMSUB132SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2077 …HECK: $xmm0 = VFNMSUB132SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2078 …m0 = VFNMSUB132SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2079 …HECK: $xmm0 = VFNMSUB132SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2080 …m0 = VFNMSUB132SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2081 ; CHECK: $xmm0 = VFNMSUB132SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2082 $xmm0 = VFNMSUB132SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2083 ; CHECK: $xmm0 = VFNMSUB132SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2084 $xmm0 = VFNMSUB132SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2085 …HECK: $xmm0 = VFNMSUB213SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2086 …m0 = VFNMSUB213SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2087 …HECK: $xmm0 = VFNMSUB213SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2088 …m0 = VFNMSUB213SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2089 ; CHECK: $xmm0 = VFNMSUB213SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2090 $xmm0 = VFNMSUB213SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2091 ; CHECK: $xmm0 = VFNMSUB213SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2092 $xmm0 = VFNMSUB213SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2093 …HECK: $xmm0 = VFNMSUB213SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2094 …m0 = VFNMSUB213SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2095 …HECK: $xmm0 = VFNMSUB213SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2096 …m0 = VFNMSUB213SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2097 ; CHECK: $xmm0 = VFNMSUB213SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2098 $xmm0 = VFNMSUB213SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2099 ; CHECK: $xmm0 = VFNMSUB213SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2100 $xmm0 = VFNMSUB213SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2101 …HECK: $xmm0 = VFNMSUB231SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2102 …m0 = VFNMSUB231SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2103 …HECK: $xmm0 = VFNMSUB231SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2104 …m0 = VFNMSUB231SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2105 ; CHECK: $xmm0 = VFNMSUB231SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2106 $xmm0 = VFNMSUB231SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2107 ; CHECK: $xmm0 = VFNMSUB231SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2108 $xmm0 = VFNMSUB231SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2109 …HECK: $xmm0 = VFNMSUB231SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2110 …m0 = VFNMSUB231SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2111 …HECK: $xmm0 = VFNMSUB231SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2112 …m0 = VFNMSUB231SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2113 ; CHECK: $xmm0 = VFNMSUB231SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2114 $xmm0 = VFNMSUB231SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2115 ; CHECK: $xmm0 = VFNMSUB231SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2116 $xmm0 = VFNMSUB231SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2151 ; CHECK: $xmm0 = VSQRTSDm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2152 $xmm0 = VSQRTSDZm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2153 ; CHECK: $xmm0 = VSQRTSDm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2154 $xmm0 = VSQRTSDZm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2155 ; CHECK: $xmm0 = VSQRTSDr $xmm0, $xmm0, implicit $mxcsr
2156 $xmm0 = VSQRTSDZr $xmm0, $xmm0, implicit $mxcsr
2157 ; CHECK: $xmm0 = VSQRTSDr_Int $xmm0, $xmm0, implicit $mxcsr
2158 $xmm0 = VSQRTSDZr_Int $xmm0, $xmm0, implicit $mxcsr
2159 ; CHECK: $xmm0 = VSQRTSSm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2160 $xmm0 = VSQRTSSZm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2161 ; CHECK: $xmm0 = VSQRTSSm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2162 $xmm0 = VSQRTSSZm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2163 ; CHECK: $xmm0 = VSQRTSSr $xmm0, $xmm1, implicit $mxcsr
2164 $xmm0 = VSQRTSSZr $xmm0, $xmm1, implicit $mxcsr
2165 ; CHECK: $xmm0 = VSQRTSSr_Int $xmm0, $xmm1, implicit $mxcsr
2166 $xmm0 = VSQRTSSZr_Int $xmm0, $xmm1, implicit $mxcsr
2167 ; CHECK: $rdi = VCVTSD2SI64rr_Int $xmm0, implicit $mxcsr
2168 $rdi = VCVTSD2SI64Zrr_Int $xmm0, implicit $mxcsr
2169 ; CHECK: $edi = VCVTSD2SIrr_Int $xmm0, implicit $mxcsr
2170 $edi = VCVTSD2SIZrr_Int $xmm0, implicit $mxcsr
2171 ; CHECK: $xmm0 = VCVTSD2SSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2172 $xmm0 = VCVTSD2SSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2173 ; CHECK: $xmm0 = VCVTSD2SSrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2174 $xmm0 = VCVTSD2SSZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2175 ; CHECK: $xmm0 = VCVTSD2SSrr $xmm0, $xmm1, implicit $mxcsr
2176 $xmm0 = VCVTSD2SSZrr $xmm0, $xmm1, implicit $mxcsr
2177 ; CHECK: $xmm0 = VCVTSD2SSrr_Int $xmm0, $xmm1, implicit $mxcsr
2178 $xmm0 = VCVTSD2SSZrr_Int $xmm0, $xmm1, implicit $mxcsr
2187 ; CHECK: $xmm0 = VCVTSI2SSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2188 $xmm0 = VCVTSI2SSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2189 ; CHECK: $xmm0 = VCVTSI2SSrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2190 $xmm0 = VCVTSI2SSZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2191 ; CHECK: $xmm0 = VCVTSI2SSrr $xmm0, $edi, implicit $mxcsr
2192 $xmm0 = VCVTSI2SSZrr $xmm0, $edi, implicit $mxcsr
2193 ; CHECK: $xmm0 = VCVTSI2SSrr_Int $xmm0, $edi, implicit $mxcsr
2194 $xmm0 = VCVTSI2SSZrr_Int $xmm0, $edi, implicit $mxcsr
2195 ; CHECK: $xmm0 = VCVTSI642SDrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2196 $xmm0 = VCVTSI642SDZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2197 ; CHECK: $xmm0 = VCVTSI642SDrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2198 $xmm0 = VCVTSI642SDZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2199 ; CHECK: $xmm0 = VCVTSI642SDrr $xmm0, $rdi, implicit $mxcsr
2200 $xmm0 = VCVTSI642SDZrr $xmm0, $rdi, implicit $mxcsr
2201 ; CHECK: $xmm0 = VCVTSI642SDrr_Int $xmm0, $rdi, implicit $mxcsr
2202 $xmm0 = VCVTSI642SDZrr_Int $xmm0, $rdi, implicit $mxcsr
2203 ; CHECK: $xmm0 = VCVTSI642SSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2204 $xmm0 = VCVTSI642SSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2205 ; CHECK: $xmm0 = VCVTSI642SSrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2206 $xmm0 = VCVTSI642SSZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2207 ; CHECK: $xmm0 = VCVTSI642SSrr $xmm0, $rdi, implicit $mxcsr
2208 $xmm0 = VCVTSI642SSZrr $xmm0, $rdi, implicit $mxcsr
2209 ; CHECK: $xmm0 = VCVTSI642SSrr_Int $xmm0, $rdi, implicit $mxcsr
2210 $xmm0 = VCVTSI642SSZrr_Int $xmm0, $rdi, implicit $mxcsr
2211 ; CHECK: $xmm0 = VCVTSS2SDrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2212 $xmm0 = VCVTSS2SDZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2213 ; CHECK: $xmm0 = VCVTSS2SDrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2214 $xmm0 = VCVTSS2SDZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2215 ; CHECK: $xmm0 = VCVTSS2SDrr $xmm0, $xmm1, implicit $mxcsr
2216 $xmm0 = VCVTSS2SDZrr $xmm0, $xmm1, implicit $mxcsr
2217 ; CHECK: $xmm0 = VCVTSS2SDrr_Int $xmm0, $xmm1, implicit $mxcsr
2218 $xmm0 = VCVTSS2SDZrr_Int $xmm0, $xmm1, implicit $mxcsr
2219 ; CHECK: $rdi = VCVTSS2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2220 $rdi = VCVTSS2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2221 ; CHECK: $rdi = VCVTSS2SI64rr_Int $xmm0, implicit $mxcsr
2222 $rdi = VCVTSS2SI64Zrr_Int $xmm0, implicit $mxcsr
2223 ; CHECK: $edi = VCVTSS2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2224 $edi = VCVTSS2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2225 ; CHECK: $edi = VCVTSS2SIrr_Int $xmm0, implicit $mxcsr
2226 $edi = VCVTSS2SIZrr_Int $xmm0, implicit $mxcsr
2227 ; CHECK: $rdi = VCVTTSD2SI64rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2228 $rdi = VCVTTSD2SI64Zrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2229 ; CHECK: $rdi = VCVTTSD2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2230 $rdi = VCVTTSD2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2231 ; CHECK: $rdi = VCVTTSD2SI64rr $xmm0, implicit $mxcsr
2232 $rdi = VCVTTSD2SI64Zrr $xmm0, implicit $mxcsr
2233 ; CHECK: $rdi = VCVTTSD2SI64rr_Int $xmm0, implicit $mxcsr
2234 $rdi = VCVTTSD2SI64Zrr_Int $xmm0, implicit $mxcsr
2235 ; CHECK: $edi = VCVTTSD2SIrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2236 $edi = VCVTTSD2SIZrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2237 ; CHECK: $edi = VCVTTSD2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2238 $edi = VCVTTSD2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2239 ; CHECK: $edi = VCVTTSD2SIrr $xmm0, implicit $mxcsr
2240 $edi = VCVTTSD2SIZrr $xmm0, implicit $mxcsr
2241 ; CHECK: $edi = VCVTTSD2SIrr_Int $xmm0, implicit $mxcsr
2242 $edi = VCVTTSD2SIZrr_Int $xmm0, implicit $mxcsr
2243 ; CHECK: $rdi = VCVTTSS2SI64rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2244 $rdi = VCVTTSS2SI64Zrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2245 ; CHECK: $rdi = VCVTTSS2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2246 $rdi = VCVTTSS2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2247 ; CHECK: $rdi = VCVTTSS2SI64rr $xmm0, implicit $mxcsr
2248 $rdi = VCVTTSS2SI64Zrr $xmm0, implicit $mxcsr
2249 ; CHECK: $rdi = VCVTTSS2SI64rr_Int $xmm0, implicit $mxcsr
2250 $rdi = VCVTTSS2SI64Zrr_Int $xmm0, implicit $mxcsr
2251 ; CHECK: $edi = VCVTTSS2SIrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2252 $edi = VCVTTSS2SIZrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2253 ; CHECK: $edi = VCVTTSS2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2254 $edi = VCVTTSS2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2255 ; CHECK: $edi = VCVTTSS2SIrr $xmm0, implicit $mxcsr
2256 $edi = VCVTTSS2SIZrr $xmm0, implicit $mxcsr
2257 ; CHECK: $edi = VCVTTSS2SIrr_Int $xmm0, implicit $mxcsr
2258 $edi = VCVTTSS2SIZrr_Int $xmm0, implicit $mxcsr
2317 …_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2318 … $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2319 ; CHECK: VCOMISDrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2320 VCOMISDZrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2321 …_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2322 … $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2323 ; CHECK: VCOMISSrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2324 VCOMISSZrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2325 …m_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2326 … $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2327 ; CHECK: VUCOMISDrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2328 VUCOMISDZrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2329 …m_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2330 … $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2331 ; CHECK: VUCOMISSrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2332 VUCOMISSZrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2333 … $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2334 … $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2335 ; CHECK: VCOMISDrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2336 VCOMISDZrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2337 … $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2338 … $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2339 ; CHECK: VCOMISSrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2340 VCOMISSZrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2341 …m $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2342 … $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2343 ; CHECK: VUCOMISDrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2344 VUCOMISDZrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2345 …m $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2346 … $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2347 ; CHECK: VUCOMISSrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2348 VUCOMISSZrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2357 …; CHECK: $xmm0 = VROUNDSDm $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2358 …$xmm0 = VRNDSCALESDZm $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2359 ; CHECK: $xmm0 = VROUNDSDr $xmm0, $xmm1, 15, implicit $mxcsr
2360 $xmm0 = VRNDSCALESDZr $xmm0, $xmm1, 15, implicit $mxcsr
2361 …; CHECK: $xmm0 = VROUNDSSm $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2362 …$xmm0 = VRNDSCALESSZm $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2363 ; CHECK: $xmm0 = VROUNDSSr $xmm0, $xmm1, 15, implicit $mxcsr
2364 $xmm0 = VRNDSCALESSZr $xmm0, $xmm1, 15, implicit $mxcsr
2365 …; CHECK: $xmm0 = VROUNDSDm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2366 …$xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2367 ; CHECK: $xmm0 = VROUNDSDr_Int $xmm0, $xmm1, 15, implicit $mxcsr
2368 $xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 15, implicit $mxcsr
2369 …; CHECK: $xmm0 = VROUNDSSm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2370 …$xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2371 ; CHECK: $xmm0 = VROUNDSSr_Int $xmm0, $xmm1, 15, implicit $mxcsr
2372 $xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 15, implicit $mxcsr
2533 ; CHECK: $ymm16 = VMULPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2534 $ymm16 = VMULPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2535 ; CHECK: $ymm16 = VMULPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2536 $ymm16 = VMULPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2537 ; CHECK: $ymm16 = VMULPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2538 $ymm16 = VMULPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2539 ; CHECK: $ymm16 = VMULPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2540 $ymm16 = VMULPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2681 ; CHECK: $ymm16 = VADDPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2682 $ymm16 = VADDPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2683 ; CHECK: $ymm16 = VADDPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2684 $ymm16 = VADDPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2685 ; CHECK: $ymm16 = VADDPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2686 $ymm16 = VADDPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2687 ; CHECK: $ymm16 = VADDPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2688 $ymm16 = VADDPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2705 ; CHECK: $ymm16 = VDIVPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2706 $ymm16 = VDIVPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2707 ; CHECK: $ymm16 = VDIVPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2708 $ymm16 = VDIVPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2709 ; CHECK: $ymm16 = VDIVPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2710 $ymm16 = VDIVPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2711 ; CHECK: $ymm16 = VDIVPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2712 $ymm16 = VDIVPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2713 ; CHECK: $ymm16 = VMAXCPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2714 $ymm16 = VMAXCPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2715 ; CHECK: $ymm16 = VMAXCPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2716 $ymm16 = VMAXCPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2717 ; CHECK: $ymm16 = VMAXCPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2718 $ymm16 = VMAXCPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2719 ; CHECK: $ymm16 = VMAXCPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2720 $ymm16 = VMAXCPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2721 ; CHECK: $ymm16 = VMAXPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2722 $ymm16 = VMAXPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2723 ; CHECK: $ymm16 = VMAXPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2724 $ymm16 = VMAXPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2725 ; CHECK: $ymm16 = VMAXPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2726 $ymm16 = VMAXPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2727 ; CHECK: $ymm16 = VMAXPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2728 $ymm16 = VMAXPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2729 ; CHECK: $ymm16 = VMINCPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2730 $ymm16 = VMINCPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2731 ; CHECK: $ymm16 = VMINCPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2732 $ymm16 = VMINCPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2733 ; CHECK: $ymm16 = VMINCPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2734 $ymm16 = VMINCPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2735 ; CHECK: $ymm16 = VMINCPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2736 $ymm16 = VMINCPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2737 ; CHECK: $ymm16 = VMINPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2738 $ymm16 = VMINPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2739 ; CHECK: $ymm16 = VMINPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2740 $ymm16 = VMINPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2741 ; CHECK: $ymm16 = VMINPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2742 $ymm16 = VMINPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2743 ; CHECK: $ymm16 = VMINPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2744 $ymm16 = VMINPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2785 ; CHECK: $ymm16 = VSUBPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2786 $ymm16 = VSUBPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2787 ; CHECK: $ymm16 = VSUBPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2788 $ymm16 = VSUBPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2789 ; CHECK: $ymm16 = VSUBPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2790 $ymm16 = VSUBPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2791 ; CHECK: $ymm16 = VSUBPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2792 $ymm16 = VSUBPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2825 …CK: $ymm16 = VFMADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2826 …6 = VFMADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2827 ; CHECK: $ymm16 = VFMADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2828 $ymm16 = VFMADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2829 …CK: $ymm16 = VFMADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2830 …6 = VFMADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2831 ; CHECK: $ymm16 = VFMADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2832 $ymm16 = VFMADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2833 …CK: $ymm16 = VFMADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2834 …6 = VFMADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2835 ; CHECK: $ymm16 = VFMADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2836 $ymm16 = VFMADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2837 …CK: $ymm16 = VFMADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2838 …6 = VFMADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2839 ; CHECK: $ymm16 = VFMADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2840 $ymm16 = VFMADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2841 …CK: $ymm16 = VFMADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2842 …6 = VFMADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2843 ; CHECK: $ymm16 = VFMADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2844 $ymm16 = VFMADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2845 …CK: $ymm16 = VFMADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2846 …6 = VFMADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2847 ; CHECK: $ymm16 = VFMADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2848 $ymm16 = VFMADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2849 …CK: $ymm16 = VFMADDSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2850 …6 = VFMADDSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2851 ; CHECK: $ymm16 = VFMADDSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2852 $ymm16 = VFMADDSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2853 …CK: $ymm16 = VFMADDSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2854 …6 = VFMADDSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2855 ; CHECK: $ymm16 = VFMADDSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2856 $ymm16 = VFMADDSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2857 …CK: $ymm16 = VFMADDSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2858 …6 = VFMADDSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2859 ; CHECK: $ymm16 = VFMADDSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2860 $ymm16 = VFMADDSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2861 …CK: $ymm16 = VFMADDSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2862 …6 = VFMADDSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2863 ; CHECK: $ymm16 = VFMADDSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2864 $ymm16 = VFMADDSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2865 …CK: $ymm16 = VFMADDSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2866 …6 = VFMADDSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2867 ; CHECK: $ymm16 = VFMADDSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2868 $ymm16 = VFMADDSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2869 …CK: $ymm16 = VFMADDSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2870 …6 = VFMADDSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2871 ; CHECK: $ymm16 = VFMADDSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2872 $ymm16 = VFMADDSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2873 …CK: $ymm16 = VFMSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2874 …6 = VFMSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2875 ; CHECK: $ymm16 = VFMSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2876 $ymm16 = VFMSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2877 …CK: $ymm16 = VFMSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2878 …6 = VFMSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2879 ; CHECK: $ymm16 = VFMSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2880 $ymm16 = VFMSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2881 …CK: $ymm16 = VFMSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2882 …6 = VFMSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2883 ; CHECK: $ymm16 = VFMSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2884 $ymm16 = VFMSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2885 …CK: $ymm16 = VFMSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2886 …6 = VFMSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2887 ; CHECK: $ymm16 = VFMSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2888 $ymm16 = VFMSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2889 …CK: $ymm16 = VFMSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2890 …6 = VFMSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2891 ; CHECK: $ymm16 = VFMSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2892 $ymm16 = VFMSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2893 …CK: $ymm16 = VFMSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2894 …6 = VFMSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2895 ; CHECK: $ymm16 = VFMSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2896 $ymm16 = VFMSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2897 …CK: $ymm16 = VFMSUBADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2898 …6 = VFMSUBADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2899 ; CHECK: $ymm16 = VFMSUBADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2900 $ymm16 = VFMSUBADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2901 …CK: $ymm16 = VFMSUBADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2902 …6 = VFMSUBADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2903 ; CHECK: $ymm16 = VFMSUBADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2904 $ymm16 = VFMSUBADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2905 …CK: $ymm16 = VFMSUBADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2906 …6 = VFMSUBADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2907 ; CHECK: $ymm16 = VFMSUBADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2908 $ymm16 = VFMSUBADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2909 …CK: $ymm16 = VFMSUBADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2910 …6 = VFMSUBADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2911 ; CHECK: $ymm16 = VFMSUBADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2912 $ymm16 = VFMSUBADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2913 …CK: $ymm16 = VFMSUBADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2914 …6 = VFMSUBADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2915 ; CHECK: $ymm16 = VFMSUBADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2916 $ymm16 = VFMSUBADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2917 …CK: $ymm16 = VFMSUBADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2918 …6 = VFMSUBADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2919 ; CHECK: $ymm16 = VFMSUBADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2920 $ymm16 = VFMSUBADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2921 …CK: $ymm16 = VFNMADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2922 …6 = VFNMADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2923 ; CHECK: $ymm16 = VFNMADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2924 $ymm16 = VFNMADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2925 …CK: $ymm16 = VFNMADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2926 …6 = VFNMADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2927 ; CHECK: $ymm16 = VFNMADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2928 $ymm16 = VFNMADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2929 …CK: $ymm16 = VFNMADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2930 …6 = VFNMADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2931 ; CHECK: $ymm16 = VFNMADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2932 $ymm16 = VFNMADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2933 …CK: $ymm16 = VFNMADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2934 …6 = VFNMADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2935 ; CHECK: $ymm16 = VFNMADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2936 $ymm16 = VFNMADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2937 …CK: $ymm16 = VFNMADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2938 …6 = VFNMADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2939 ; CHECK: $ymm16 = VFNMADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2940 $ymm16 = VFNMADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2941 …CK: $ymm16 = VFNMADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2942 …6 = VFNMADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2943 ; CHECK: $ymm16 = VFNMADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2944 $ymm16 = VFNMADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2945 …CK: $ymm16 = VFNMSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2946 …6 = VFNMSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2947 ; CHECK: $ymm16 = VFNMSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2948 $ymm16 = VFNMSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2949 …CK: $ymm16 = VFNMSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2950 …6 = VFNMSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2951 ; CHECK: $ymm16 = VFNMSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2952 $ymm16 = VFNMSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2953 …CK: $ymm16 = VFNMSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2954 …6 = VFNMSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2955 ; CHECK: $ymm16 = VFNMSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2956 $ymm16 = VFNMSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2957 …CK: $ymm16 = VFNMSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2958 …6 = VFNMSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2959 ; CHECK: $ymm16 = VFNMSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2960 $ymm16 = VFNMSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2961 …CK: $ymm16 = VFNMSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2962 …6 = VFNMSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2963 ; CHECK: $ymm16 = VFNMSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2964 $ymm16 = VFNMSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2965 …CK: $ymm16 = VFNMSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2966 …6 = VFNMSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2967 ; CHECK: $ymm16 = VFNMSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2968 $ymm16 = VFNMSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
3176 $ymm16 = VCVTDQ2PDZ256rr $xmm0, implicit $mxcsr
3177 ; CHECK: $ymm16 = VCVTDQ2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3178 $ymm16 = VCVTDQ2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3179 ; CHECK: $ymm16 = VCVTDQ2PSZ256rr $ymm16, implicit $mxcsr
3180 $ymm16 = VCVTDQ2PSZ256rr $ymm16, implicit $mxcsr
3181 ; CHECK: $xmm16 = VCVTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3182 $xmm16 = VCVTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3183 ; CHECK: $xmm16 = VCVTPD2DQZ256rr $ymm16, implicit $mxcsr
3184 $xmm16 = VCVTPD2DQZ256rr $ymm16, implicit $mxcsr
3185 ; CHECK: $xmm16 = VCVTPD2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3186 $xmm16 = VCVTPD2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3187 ; CHECK: $xmm16 = VCVTPD2PSZ256rr $ymm16, implicit $mxcsr
3188 $xmm16 = VCVTPD2PSZ256rr $ymm16, implicit $mxcsr
3189 ; CHECK: $ymm16 = VCVTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3190 $ymm16 = VCVTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3191 ; CHECK: $ymm16 = VCVTPS2DQZ256rr $ymm16, implicit $mxcsr
3192 $ymm16 = VCVTPS2DQZ256rr $ymm16, implicit $mxcsr
3193 ; CHECK: $ymm16 = VCVTPS2PDZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3194 $ymm16 = VCVTPS2PDZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3195 ; CHECK: $ymm16 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
3196 $ymm16 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
3197 …; CHECK: VCVTPS2PHZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16, 0, implicit $mxcsr
3198 …VCVTPS2PHZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16, 0, implicit $mxcsr
3199 ; CHECK: $xmm0 = VCVTPS2PHZ256rr $ymm16, 0, implicit $mxcsr
3200 $xmm0 = VCVTPS2PHZ256rr $ymm16, 0, implicit $mxcsr
3201 ; CHECK: $ymm16 = VCVTPH2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3202 $ymm16 = VCVTPH2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3203 ; CHECK: $ymm16 = VCVTPH2PSZ256rr $xmm16, implicit $mxcsr
3204 $ymm16 = VCVTPH2PSZ256rr $xmm16, implicit $mxcsr
3205 ; CHECK: $xmm16 = VCVTTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3206 $xmm16 = VCVTTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3207 ; CHECK: $xmm16 = VCVTTPD2DQZ256rr $ymm16, implicit $mxcsr
3208 $xmm16 = VCVTTPD2DQZ256rr $ymm16, implicit $mxcsr
3209 ; CHECK: $ymm16 = VCVTTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3210 $ymm16 = VCVTTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3211 ; CHECK: $ymm16 = VCVTTPS2DQZ256rr $ymm16, implicit $mxcsr
3212 $ymm16 = VCVTTPS2DQZ256rr $ymm16, implicit $mxcsr
3213 ; CHECK: $ymm16 = VSQRTPDZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3214 $ymm16 = VSQRTPDZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3215 ; CHECK: $ymm16 = VSQRTPDZ256r $ymm16, implicit $mxcsr
3216 $ymm16 = VSQRTPDZ256r $ymm16, implicit $mxcsr
3217 ; CHECK: $ymm16 = VSQRTPSZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3218 $ymm16 = VSQRTPSZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3219 ; CHECK: $ymm16 = VSQRTPSZ256r $ymm16, implicit $mxcsr
3220 $ymm16 = VSQRTPSZ256r $ymm16, implicit $mxcsr
3255 ; CHECK: $ymm16 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
3256 $ymm16 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
3257 ; CHECK: $ymm16 = VRNDSCALEPDZ256rri $ymm16, 15, implicit $mxcsr
3258 $ymm16 = VRNDSCALEPDZ256rri $ymm16, 15, implicit $mxcsr
3259 ; CHECK: $ymm16 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
3260 $ymm16 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
3261 ; CHECK: $ymm16 = VRNDSCALEPSZ256rri $ymm16, 15, implicit $mxcsr
3262 $ymm16 = VRNDSCALEPSZ256rri $ymm16, 15, implicit $mxcsr
3263 ; CHECK: $ymm0 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
3264 $ymm0 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
3265 ; CHECK: $ymm0 = VRNDSCALEPDZ256rri $ymm0, 31, implicit $mxcsr
3266 $ymm0 = VRNDSCALEPDZ256rri $ymm0, 31, implicit $mxcsr
3267 ; CHECK: $ymm0 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
3268 $ymm0 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
3269 ; CHECK: $ymm0 = VRNDSCALEPSZ256rri $ymm0, 31, implicit $mxcsr
3270 $ymm0 = VRNDSCALEPSZ256rri $ymm0, 31, implicit $mxcsr
3449 ; CHECK: $xmm16 = VMAXCPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3450 $xmm16 = VMAXCPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3451 ; CHECK: $xmm16 = VMAXCPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3452 $xmm16 = VMAXCPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3453 ; CHECK: $xmm16 = VMAXCPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3454 $xmm16 = VMAXCPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3455 ; CHECK: $xmm16 = VMAXCPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3456 $xmm16 = VMAXCPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3457 ; CHECK: $xmm16 = VMAXPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3458 $xmm16 = VMAXPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3459 ; CHECK: $xmm16 = VMAXPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3460 $xmm16 = VMAXPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3461 ; CHECK: $xmm16 = VMAXPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3462 $xmm16 = VMAXPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3463 ; CHECK: $xmm16 = VMAXPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3464 $xmm16 = VMAXPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3465 ; CHECK: $xmm16 = VMINCPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3466 $xmm16 = VMINCPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3467 ; CHECK: $xmm16 = VMINCPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3468 $xmm16 = VMINCPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3469 ; CHECK: $xmm16 = VMINCPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3470 $xmm16 = VMINCPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3471 ; CHECK: $xmm16 = VMINCPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3472 $xmm16 = VMINCPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3473 ; CHECK: $xmm16 = VMINPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3474 $xmm16 = VMINPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3475 ; CHECK: $xmm16 = VMINPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3476 $xmm16 = VMINPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3477 ; CHECK: $xmm16 = VMINPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3478 $xmm16 = VMINPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3479 ; CHECK: $xmm16 = VMINPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3480 $xmm16 = VMINPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3481 ; CHECK: $xmm16 = VMULPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3482 $xmm16 = VMULPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3483 ; CHECK: $xmm16 = VMULPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3484 $xmm16 = VMULPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3485 ; CHECK: $xmm16 = VMULPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3486 $xmm16 = VMULPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3487 ; CHECK: $xmm16 = VMULPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3488 $xmm16 = VMULPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3669 ; CHECK: $xmm16 = VADDPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3670 $xmm16 = VADDPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3671 ; CHECK: $xmm16 = VADDPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3672 $xmm16 = VADDPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3673 ; CHECK: $xmm16 = VADDPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3674 $xmm16 = VADDPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3675 ; CHECK: $xmm16 = VADDPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3676 $xmm16 = VADDPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3693 ; CHECK: $xmm16 = VDIVPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3694 $xmm16 = VDIVPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3695 ; CHECK: $xmm16 = VDIVPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3696 $xmm16 = VDIVPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3697 ; CHECK: $xmm16 = VDIVPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3698 $xmm16 = VDIVPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3699 ; CHECK: $xmm16 = VDIVPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3700 $xmm16 = VDIVPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3709 ; CHECK: $xmm16 = VSUBPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3710 $xmm16 = VSUBPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3711 ; CHECK: $xmm16 = VSUBPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3712 $xmm16 = VSUBPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3713 ; CHECK: $xmm16 = VSUBPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3714 $xmm16 = VSUBPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3715 ; CHECK: $xmm16 = VSUBPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3716 $xmm16 = VSUBPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3797 …CK: $xmm16 = VFMADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3798 …6 = VFMADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3799 ; CHECK: $xmm16 = VFMADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3800 $xmm16 = VFMADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3801 …CK: $xmm16 = VFMADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3802 …6 = VFMADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3803 ; CHECK: $xmm16 = VFMADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3804 $xmm16 = VFMADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3805 …CK: $xmm16 = VFMADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3806 …6 = VFMADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3807 ; CHECK: $xmm16 = VFMADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3808 $xmm16 = VFMADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3809 …CK: $xmm16 = VFMADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3810 …6 = VFMADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3811 ; CHECK: $xmm16 = VFMADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3812 $xmm16 = VFMADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3813 …CK: $xmm16 = VFMADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3814 …6 = VFMADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3815 ; CHECK: $xmm16 = VFMADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3816 $xmm16 = VFMADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3817 …CK: $xmm16 = VFMADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3818 …6 = VFMADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3819 ; CHECK: $xmm16 = VFMADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3820 $xmm16 = VFMADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3821 …CK: $xmm16 = VFMADDSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3822 …6 = VFMADDSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3823 ; CHECK: $xmm16 = VFMADDSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3824 $xmm16 = VFMADDSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3825 …CK: $xmm16 = VFMADDSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3826 …6 = VFMADDSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3827 ; CHECK: $xmm16 = VFMADDSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3828 $xmm16 = VFMADDSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3829 …CK: $xmm16 = VFMADDSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3830 …6 = VFMADDSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3831 ; CHECK: $xmm16 = VFMADDSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3832 $xmm16 = VFMADDSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3833 …CK: $xmm16 = VFMADDSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3834 …6 = VFMADDSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3835 ; CHECK: $xmm16 = VFMADDSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3836 $xmm16 = VFMADDSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3837 …CK: $xmm16 = VFMADDSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3838 …6 = VFMADDSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3839 ; CHECK: $xmm16 = VFMADDSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3840 $xmm16 = VFMADDSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3841 …CK: $xmm16 = VFMADDSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3842 …6 = VFMADDSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3843 ; CHECK: $xmm16 = VFMADDSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3844 $xmm16 = VFMADDSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3845 …CK: $xmm16 = VFMSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3846 …6 = VFMSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3847 ; CHECK: $xmm16 = VFMSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3848 $xmm16 = VFMSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3849 …CK: $xmm16 = VFMSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3850 …6 = VFMSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3851 ; CHECK: $xmm16 = VFMSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3852 $xmm16 = VFMSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3853 …CK: $xmm16 = VFMSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3854 …6 = VFMSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3855 ; CHECK: $xmm16 = VFMSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3856 $xmm16 = VFMSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3857 …CK: $xmm16 = VFMSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3858 …6 = VFMSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3859 ; CHECK: $xmm16 = VFMSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3860 $xmm16 = VFMSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3861 …CK: $xmm16 = VFMSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3862 …6 = VFMSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3863 ; CHECK: $xmm16 = VFMSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3864 $xmm16 = VFMSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3865 …CK: $xmm16 = VFMSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3866 …6 = VFMSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3867 ; CHECK: $xmm16 = VFMSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3868 $xmm16 = VFMSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3869 …CK: $xmm16 = VFMSUBADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3870 …6 = VFMSUBADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3871 ; CHECK: $xmm16 = VFMSUBADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3872 $xmm16 = VFMSUBADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3873 …CK: $xmm16 = VFMSUBADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3874 …6 = VFMSUBADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3875 ; CHECK: $xmm16 = VFMSUBADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3876 $xmm16 = VFMSUBADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3877 …CK: $xmm16 = VFMSUBADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3878 …6 = VFMSUBADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3879 ; CHECK: $xmm16 = VFMSUBADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3880 $xmm16 = VFMSUBADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3881 …CK: $xmm16 = VFMSUBADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3882 …6 = VFMSUBADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3883 ; CHECK: $xmm16 = VFMSUBADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3884 $xmm16 = VFMSUBADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3885 …CK: $xmm16 = VFMSUBADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3886 …6 = VFMSUBADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3887 ; CHECK: $xmm16 = VFMSUBADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3888 $xmm16 = VFMSUBADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3889 …CK: $xmm16 = VFMSUBADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3890 …6 = VFMSUBADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3891 ; CHECK: $xmm16 = VFMSUBADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3892 $xmm16 = VFMSUBADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3893 …CK: $xmm16 = VFNMADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3894 …6 = VFNMADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3895 ; CHECK: $xmm16 = VFNMADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3896 $xmm16 = VFNMADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3897 …CK: $xmm16 = VFNMADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3898 …6 = VFNMADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3899 ; CHECK: $xmm16 = VFNMADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3900 $xmm16 = VFNMADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3901 …CK: $xmm16 = VFNMADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3902 …6 = VFNMADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3903 ; CHECK: $xmm16 = VFNMADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3904 $xmm16 = VFNMADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3905 …CK: $xmm16 = VFNMADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3906 …6 = VFNMADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3907 ; CHECK: $xmm16 = VFNMADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3908 $xmm16 = VFNMADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3909 …CK: $xmm16 = VFNMADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3910 …6 = VFNMADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3911 ; CHECK: $xmm16 = VFNMADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3912 $xmm16 = VFNMADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3913 …CK: $xmm16 = VFNMADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3914 …6 = VFNMADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3915 ; CHECK: $xmm16 = VFNMADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3916 $xmm16 = VFNMADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3917 …CK: $xmm16 = VFNMSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3918 …6 = VFNMSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3919 ; CHECK: $xmm16 = VFNMSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3920 $xmm16 = VFNMSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3921 …CK: $xmm16 = VFNMSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3922 …6 = VFNMSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3923 ; CHECK: $xmm16 = VFNMSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3924 $xmm16 = VFNMSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3925 …CK: $xmm16 = VFNMSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3926 …6 = VFNMSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3927 ; CHECK: $xmm16 = VFNMSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3928 $xmm16 = VFNMSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3929 …CK: $xmm16 = VFNMSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3930 …6 = VFNMSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3931 ; CHECK: $xmm16 = VFNMSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3932 $xmm16 = VFNMSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3933 …CK: $xmm16 = VFNMSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3934 …6 = VFNMSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3935 ; CHECK: $xmm16 = VFNMSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3936 $xmm16 = VFNMSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3937 …CK: $xmm16 = VFNMSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3938 …6 = VFNMSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3939 ; CHECK: $xmm16 = VFNMSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3940 $xmm16 = VFNMSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
4027 ; CHECK: $xmm16 = VCVTPH2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4028 $xmm16 = VCVTPH2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4029 ; CHECK: $xmm16 = VCVTPH2PSZ128rr $xmm16, implicit $mxcsr
4030 $xmm16 = VCVTPH2PSZ128rr $xmm16, implicit $mxcsr
4035 ; CHECK: $xmm16 = VCVTDQ2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4036 $xmm16 = VCVTDQ2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4037 ; CHECK: $xmm16 = VCVTDQ2PSZ128rr $xmm16, implicit $mxcsr
4038 $xmm16 = VCVTDQ2PSZ128rr $xmm16, implicit $mxcsr
4039 ; CHECK: $xmm16 = VCVTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4040 $xmm16 = VCVTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4041 ; CHECK: $xmm16 = VCVTPD2DQZ128rr $xmm16, implicit $mxcsr
4042 $xmm16 = VCVTPD2DQZ128rr $xmm16, implicit $mxcsr
4043 ; CHECK: $xmm16 = VCVTPD2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4044 $xmm16 = VCVTPD2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4045 ; CHECK: $xmm16 = VCVTPD2PSZ128rr $xmm16, implicit $mxcsr
4046 $xmm16 = VCVTPD2PSZ128rr $xmm16, implicit $mxcsr
4047 ; CHECK: $xmm16 = VCVTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4048 $xmm16 = VCVTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4049 ; CHECK: $xmm16 = VCVTPS2DQZ128rr $xmm16, implicit $mxcsr
4050 $xmm16 = VCVTPS2DQZ128rr $xmm16, implicit $mxcsr
4051 ; CHECK: $xmm16 = VCVTPS2PDZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4052 $xmm16 = VCVTPS2PDZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4053 ; CHECK: $xmm16 = VCVTPS2PDZ128rr $xmm16, implicit $mxcsr
4054 $xmm16 = VCVTPS2PDZ128rr $xmm16, implicit $mxcsr
4055 ; CHECK: $xmm16 = VCVTTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4056 $xmm16 = VCVTTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4057 ; CHECK: $xmm16 = VCVTTPD2DQZ128rr $xmm16, implicit $mxcsr
4058 $xmm16 = VCVTTPD2DQZ128rr $xmm16, implicit $mxcsr
4059 ; CHECK: $xmm16 = VCVTTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4060 $xmm16 = VCVTTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4061 ; CHECK: $xmm16 = VCVTTPS2DQZ128rr $xmm16, implicit $mxcsr
4062 $xmm16 = VCVTTPS2DQZ128rr $xmm16, implicit $mxcsr
4063 ; CHECK: $xmm16 = VSQRTPDZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4064 $xmm16 = VSQRTPDZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4065 ; CHECK: $xmm16 = VSQRTPDZ128r $xmm16, implicit $mxcsr
4066 $xmm16 = VSQRTPDZ128r $xmm16, implicit $mxcsr
4067 ; CHECK: $xmm16 = VSQRTPSZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4068 $xmm16 = VSQRTPSZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4069 ; CHECK: $xmm16 = VSQRTPSZ128r $xmm16, implicit $mxcsr
4070 $xmm16 = VSQRTPSZ128r $xmm16, implicit $mxcsr
4137 ; CHECK: $xmm16 = VCVTPS2PHZ128rr $xmm16, 2, implicit $mxcsr
4138 $xmm16 = VCVTPS2PHZ128rr $xmm16, 2, implicit $mxcsr
4139 …; CHECK: VCVTPS2PHZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16, 2, implicit $mxcsr
4140 …VCVTPS2PHZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16, 2, implicit $mxcsr
4165 ; CHECK: $xmm16 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4166 $xmm16 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4167 ; CHECK: $xmm16 = VRNDSCALEPDZ128rri $xmm16, 15, implicit $mxcsr
4168 $xmm16 = VRNDSCALEPDZ128rri $xmm16, 15, implicit $mxcsr
4169 ; CHECK: $xmm16 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4170 $xmm16 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4171 ; CHECK: $xmm16 = VRNDSCALEPSZ128rri $xmm16, 15, implicit $mxcsr
4172 $xmm16 = VRNDSCALEPSZ128rri $xmm16, 15, implicit $mxcsr
4173 ; CHECK: $xmm0 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4174 $xmm0 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4175 ; CHECK: $xmm0 = VRNDSCALEPDZ128rri $xmm0, 31, implicit $mxcsr
4176 $xmm0 = VRNDSCALEPDZ128rri $xmm0, 31, implicit $mxcsr
4177 ; CHECK: $xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4178 $xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4179 ; CHECK: $xmm0 = VRNDSCALEPSZ128rri $xmm0, 31, implicit $mxcsr
4180 $xmm0 = VRNDSCALEPSZ128rri $xmm0, 31, implicit $mxcsr
4191 ; CHECK: $xmm16 = VADDSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4192 $xmm16 = VADDSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4193 ; CHECK: $xmm16 = VADDSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4194 $xmm16 = VADDSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4195 ; CHECK: $xmm16 = VADDSDZrr $xmm16, $xmm1, implicit $mxcsr
4196 $xmm16 = VADDSDZrr $xmm16, $xmm1, implicit $mxcsr
4197 ; CHECK: $xmm16 = VADDSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4198 $xmm16 = VADDSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4199 ; CHECK: $xmm16 = VADDSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4200 $xmm16 = VADDSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4201 ; CHECK: $xmm16 = VADDSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4202 $xmm16 = VADDSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4203 ; CHECK: $xmm16 = VADDSSZrr $xmm16, $xmm1, implicit $mxcsr
4204 $xmm16 = VADDSSZrr $xmm16, $xmm1, implicit $mxcsr
4205 ; CHECK: $xmm16 = VADDSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4206 $xmm16 = VADDSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4207 ; CHECK: $xmm16 = VDIVSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4208 $xmm16 = VDIVSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4209 ; CHECK: $xmm16 = VDIVSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4210 $xmm16 = VDIVSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4211 ; CHECK: $xmm16 = VDIVSDZrr $xmm16, $xmm1, implicit $mxcsr
4212 $xmm16 = VDIVSDZrr $xmm16, $xmm1, implicit $mxcsr
4213 ; CHECK: $xmm16 = VDIVSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4214 $xmm16 = VDIVSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4215 ; CHECK: $xmm16 = VDIVSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4216 $xmm16 = VDIVSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4217 ; CHECK: $xmm16 = VDIVSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4218 $xmm16 = VDIVSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4219 ; CHECK: $xmm16 = VDIVSSZrr $xmm16, $xmm1, implicit $mxcsr
4220 $xmm16 = VDIVSSZrr $xmm16, $xmm1, implicit $mxcsr
4221 ; CHECK: $xmm16 = VDIVSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4222 $xmm16 = VDIVSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4223 ; CHECK: $xmm16 = VMAXCSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4224 $xmm16 = VMAXCSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4225 ; CHECK: $xmm16 = VMAXCSDZrr $xmm16, $xmm1, implicit $mxcsr
4226 $xmm16 = VMAXCSDZrr $xmm16, $xmm1, implicit $mxcsr
4227 ; CHECK: $xmm16 = VMAXCSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4228 $xmm16 = VMAXCSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4229 ; CHECK: $xmm16 = VMAXCSSZrr $xmm16, $xmm1, implicit $mxcsr
4230 $xmm16 = VMAXCSSZrr $xmm16, $xmm1, implicit $mxcsr
4231 ; CHECK: $xmm16 = VMAXSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4232 $xmm16 = VMAXSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4233 ; CHECK: $xmm16 = VMAXSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4234 $xmm16 = VMAXSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4235 ; CHECK: $xmm16 = VMAXSDZrr $xmm16, $xmm1, implicit $mxcsr
4236 $xmm16 = VMAXSDZrr $xmm16, $xmm1, implicit $mxcsr
4237 ; CHECK: $xmm16 = VMAXSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4238 $xmm16 = VMAXSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4239 ; CHECK: $xmm16 = VMAXSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4240 $xmm16 = VMAXSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4241 ; CHECK: $xmm16 = VMAXSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4242 $xmm16 = VMAXSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4243 ; CHECK: $xmm16 = VMAXSSZrr $xmm16, $xmm1, implicit $mxcsr
4244 $xmm16 = VMAXSSZrr $xmm16, $xmm1, implicit $mxcsr
4245 ; CHECK: $xmm16 = VMAXSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4246 $xmm16 = VMAXSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4247 ; CHECK: $xmm16 = VMINCSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4248 $xmm16 = VMINCSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4249 ; CHECK: $xmm16 = VMINCSDZrr $xmm16, $xmm1, implicit $mxcsr
4250 $xmm16 = VMINCSDZrr $xmm16, $xmm1, implicit $mxcsr
4251 ; CHECK: $xmm16 = VMINCSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4252 $xmm16 = VMINCSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4253 ; CHECK: $xmm16 = VMINCSSZrr $xmm16, $xmm1, implicit $mxcsr
4254 $xmm16 = VMINCSSZrr $xmm16, $xmm1, implicit $mxcsr
4255 ; CHECK: $xmm16 = VMINSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4256 $xmm16 = VMINSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4257 ; CHECK: $xmm16 = VMINSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4258 $xmm16 = VMINSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4259 ; CHECK: $xmm16 = VMINSDZrr $xmm16, $xmm1, implicit $mxcsr
4260 $xmm16 = VMINSDZrr $xmm16, $xmm1, implicit $mxcsr
4261 ; CHECK: $xmm16 = VMINSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4262 $xmm16 = VMINSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4263 ; CHECK: $xmm16 = VMINSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4264 $xmm16 = VMINSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4265 ; CHECK: $xmm16 = VMINSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4266 $xmm16 = VMINSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4267 ; CHECK: $xmm16 = VMINSSZrr $xmm16, $xmm1, implicit $mxcsr
4268 $xmm16 = VMINSSZrr $xmm16, $xmm1, implicit $mxcsr
4269 ; CHECK: $xmm16 = VMINSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4270 $xmm16 = VMINSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4271 ; CHECK: $xmm16 = VMULSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4272 $xmm16 = VMULSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4273 ; CHECK: $xmm16 = VMULSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4274 $xmm16 = VMULSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4275 ; CHECK: $xmm16 = VMULSDZrr $xmm16, $xmm1, implicit $mxcsr
4276 $xmm16 = VMULSDZrr $xmm16, $xmm1, implicit $mxcsr
4277 ; CHECK: $xmm16 = VMULSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4278 $xmm16 = VMULSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4279 ; CHECK: $xmm16 = VMULSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4280 $xmm16 = VMULSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4281 ; CHECK: $xmm16 = VMULSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4282 $xmm16 = VMULSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4283 ; CHECK: $xmm16 = VMULSSZrr $xmm16, $xmm1, implicit $mxcsr
4284 $xmm16 = VMULSSZrr $xmm16, $xmm1, implicit $mxcsr
4285 ; CHECK: $xmm16 = VMULSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4286 $xmm16 = VMULSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4287 ; CHECK: $xmm16 = VSUBSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4288 $xmm16 = VSUBSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4289 ; CHECK: $xmm16 = VSUBSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4290 $xmm16 = VSUBSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4291 ; CHECK: $xmm16 = VSUBSDZrr $xmm16, $xmm1, implicit $mxcsr
4292 $xmm16 = VSUBSDZrr $xmm16, $xmm1, implicit $mxcsr
4293 ; CHECK: $xmm16 = VSUBSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4294 $xmm16 = VSUBSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4295 ; CHECK: $xmm16 = VSUBSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4296 $xmm16 = VSUBSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4297 ; CHECK: $xmm16 = VSUBSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4298 $xmm16 = VSUBSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4299 ; CHECK: $xmm16 = VSUBSSZrr $xmm16, $xmm1, implicit $mxcsr
4300 $xmm16 = VSUBSSZrr $xmm16, $xmm1, implicit $mxcsr
4301 ; CHECK: $xmm16 = VSUBSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4302 $xmm16 = VSUBSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4303 …CK: $xmm16 = VFMADD132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4304 …6 = VFMADD132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4305 …CK: $xmm16 = VFMADD132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4306 …6 = VFMADD132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4307 ; CHECK: $xmm16 = VFMADD132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4308 $xmm16 = VFMADD132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4309 ; CHECK: $xmm16 = VFMADD132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4310 $xmm16 = VFMADD132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4311 …CK: $xmm16 = VFMADD132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4312 …6 = VFMADD132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4313 …CK: $xmm16 = VFMADD132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4314 …6 = VFMADD132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4315 ; CHECK: $xmm16 = VFMADD132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4316 $xmm16 = VFMADD132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4317 ; CHECK: $xmm16 = VFMADD132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4318 $xmm16 = VFMADD132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4319 …CK: $xmm16 = VFMADD213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4320 …6 = VFMADD213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4321 …CK: $xmm16 = VFMADD213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4322 …6 = VFMADD213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4323 ; CHECK: $xmm16 = VFMADD213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4324 $xmm16 = VFMADD213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4325 ; CHECK: $xmm16 = VFMADD213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4326 $xmm16 = VFMADD213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4327 …CK: $xmm16 = VFMADD213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4328 …6 = VFMADD213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4329 …CK: $xmm16 = VFMADD213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4330 …6 = VFMADD213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4331 ; CHECK: $xmm16 = VFMADD213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4332 $xmm16 = VFMADD213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4333 ; CHECK: $xmm16 = VFMADD213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4334 $xmm16 = VFMADD213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4335 …CK: $xmm16 = VFMADD231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4336 …6 = VFMADD231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4337 …CK: $xmm16 = VFMADD231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4338 …6 = VFMADD231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4339 ; CHECK: $xmm16 = VFMADD231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4340 $xmm16 = VFMADD231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4341 ; CHECK: $xmm16 = VFMADD231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4342 $xmm16 = VFMADD231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4343 …CK: $xmm16 = VFMADD231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4344 …6 = VFMADD231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4345 …CK: $xmm16 = VFMADD231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4346 …6 = VFMADD231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4347 ; CHECK: $xmm16 = VFMADD231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4348 $xmm16 = VFMADD231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4349 ; CHECK: $xmm16 = VFMADD231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4350 $xmm16 = VFMADD231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4351 …CK: $xmm16 = VFMSUB132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4352 …6 = VFMSUB132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4353 …CK: $xmm16 = VFMSUB132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4354 …6 = VFMSUB132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4355 ; CHECK: $xmm16 = VFMSUB132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4356 $xmm16 = VFMSUB132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4357 ; CHECK: $xmm16 = VFMSUB132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4358 $xmm16 = VFMSUB132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4359 …CK: $xmm16 = VFMSUB132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4360 …6 = VFMSUB132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4361 …CK: $xmm16 = VFMSUB132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4362 …6 = VFMSUB132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4363 ; CHECK: $xmm16 = VFMSUB132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4364 $xmm16 = VFMSUB132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4365 ; CHECK: $xmm16 = VFMSUB132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4366 $xmm16 = VFMSUB132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4367 …CK: $xmm16 = VFMSUB213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4368 …6 = VFMSUB213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4369 …CK: $xmm16 = VFMSUB213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4370 …6 = VFMSUB213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4371 ; CHECK: $xmm16 = VFMSUB213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4372 $xmm16 = VFMSUB213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4373 ; CHECK: $xmm16 = VFMSUB213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4374 $xmm16 = VFMSUB213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4375 …CK: $xmm16 = VFMSUB213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4376 …6 = VFMSUB213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4377 …CK: $xmm16 = VFMSUB213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4378 …6 = VFMSUB213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4379 ; CHECK: $xmm16 = VFMSUB213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4380 $xmm16 = VFMSUB213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4381 ; CHECK: $xmm16 = VFMSUB213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4382 $xmm16 = VFMSUB213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4383 …CK: $xmm16 = VFMSUB231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4384 …6 = VFMSUB231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4385 …CK: $xmm16 = VFMSUB231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4386 …6 = VFMSUB231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4387 ; CHECK: $xmm16 = VFMSUB231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4388 $xmm16 = VFMSUB231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4389 ; CHECK: $xmm16 = VFMSUB231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4390 $xmm16 = VFMSUB231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4391 …CK: $xmm16 = VFMSUB231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4392 …6 = VFMSUB231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4393 …CK: $xmm16 = VFMSUB231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4394 …6 = VFMSUB231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4395 ; CHECK: $xmm16 = VFMSUB231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4396 $xmm16 = VFMSUB231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4397 ; CHECK: $xmm16 = VFMSUB231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4398 $xmm16 = VFMSUB231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4399 …CK: $xmm16 = VFNMADD132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4400 …6 = VFNMADD132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4401 …CK: $xmm16 = VFNMADD132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4402 …6 = VFNMADD132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4403 ; CHECK: $xmm16 = VFNMADD132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4404 $xmm16 = VFNMADD132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4405 ; CHECK: $xmm16 = VFNMADD132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4406 $xmm16 = VFNMADD132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4407 …CK: $xmm16 = VFNMADD132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4408 …6 = VFNMADD132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4409 …CK: $xmm16 = VFNMADD132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4410 …6 = VFNMADD132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4411 ; CHECK: $xmm16 = VFNMADD132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4412 $xmm16 = VFNMADD132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4413 ; CHECK: $xmm16 = VFNMADD132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4414 $xmm16 = VFNMADD132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4415 …CK: $xmm16 = VFNMADD213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4416 …6 = VFNMADD213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4417 …CK: $xmm16 = VFNMADD213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4418 …6 = VFNMADD213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4419 ; CHECK: $xmm16 = VFNMADD213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4420 $xmm16 = VFNMADD213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4421 ; CHECK: $xmm16 = VFNMADD213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4422 $xmm16 = VFNMADD213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4423 …CK: $xmm16 = VFNMADD213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4424 …6 = VFNMADD213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4425 …CK: $xmm16 = VFNMADD213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4426 …6 = VFNMADD213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4427 ; CHECK: $xmm16 = VFNMADD213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4428 $xmm16 = VFNMADD213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4429 ; CHECK: $xmm16 = VFNMADD213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4430 $xmm16 = VFNMADD213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4431 …CK: $xmm16 = VFNMADD231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4432 …6 = VFNMADD231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4433 …CK: $xmm16 = VFNMADD231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4434 …6 = VFNMADD231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4435 ; CHECK: $xmm16 = VFNMADD231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4436 $xmm16 = VFNMADD231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4437 ; CHECK: $xmm16 = VFNMADD231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4438 $xmm16 = VFNMADD231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4439 …CK: $xmm16 = VFNMADD231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4440 …6 = VFNMADD231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4441 …CK: $xmm16 = VFNMADD231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4442 …6 = VFNMADD231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4443 ; CHECK: $xmm16 = VFNMADD231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4444 $xmm16 = VFNMADD231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4445 ; CHECK: $xmm16 = VFNMADD231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4446 $xmm16 = VFNMADD231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4447 …CK: $xmm16 = VFNMSUB132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4448 …6 = VFNMSUB132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4449 …CK: $xmm16 = VFNMSUB132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4450 …6 = VFNMSUB132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4451 ; CHECK: $xmm16 = VFNMSUB132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4452 $xmm16 = VFNMSUB132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4453 ; CHECK: $xmm16 = VFNMSUB132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4454 $xmm16 = VFNMSUB132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4455 …CK: $xmm16 = VFNMSUB132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4456 …6 = VFNMSUB132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4457 …CK: $xmm16 = VFNMSUB132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4458 …6 = VFNMSUB132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4459 ; CHECK: $xmm16 = VFNMSUB132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4460 $xmm16 = VFNMSUB132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4461 ; CHECK: $xmm16 = VFNMSUB132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4462 $xmm16 = VFNMSUB132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4463 …CK: $xmm16 = VFNMSUB213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4464 …6 = VFNMSUB213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4465 …CK: $xmm16 = VFNMSUB213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4466 …6 = VFNMSUB213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4467 ; CHECK: $xmm16 = VFNMSUB213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4468 $xmm16 = VFNMSUB213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4469 ; CHECK: $xmm16 = VFNMSUB213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4470 $xmm16 = VFNMSUB213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4471 …CK: $xmm16 = VFNMSUB213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4472 …6 = VFNMSUB213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4473 …CK: $xmm16 = VFNMSUB213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4474 …6 = VFNMSUB213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4475 ; CHECK: $xmm16 = VFNMSUB213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4476 $xmm16 = VFNMSUB213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4477 ; CHECK: $xmm16 = VFNMSUB213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4478 $xmm16 = VFNMSUB213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4479 …CK: $xmm16 = VFNMSUB231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4480 …6 = VFNMSUB231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4481 …CK: $xmm16 = VFNMSUB231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4482 …6 = VFNMSUB231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4483 ; CHECK: $xmm16 = VFNMSUB231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4484 $xmm16 = VFNMSUB231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4485 ; CHECK: $xmm16 = VFNMSUB231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4486 $xmm16 = VFNMSUB231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4487 …CK: $xmm16 = VFNMSUB231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4488 …6 = VFNMSUB231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4489 …CK: $xmm16 = VFNMSUB231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4490 …6 = VFNMSUB231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4491 ; CHECK: $xmm16 = VFNMSUB231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4492 $xmm16 = VFNMSUB231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4493 ; CHECK: $xmm16 = VFNMSUB231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4494 $xmm16 = VFNMSUB231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4529 ; CHECK: $xmm16 = VSQRTSDZm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4530 $xmm16 = VSQRTSDZm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4531 ; CHECK: $xmm16 = VSQRTSDZm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4532 $xmm16 = VSQRTSDZm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4533 ; CHECK: $xmm16 = VSQRTSDZr $xmm16, $xmm1, implicit $mxcsr
4534 $xmm16 = VSQRTSDZr $xmm16, $xmm1, implicit $mxcsr
4535 ; CHECK: $xmm16 = VSQRTSDZr_Int $xmm16, $xmm1, implicit $mxcsr
4536 $xmm16 = VSQRTSDZr_Int $xmm16, $xmm1, implicit $mxcsr
4537 ; CHECK: $xmm16 = VSQRTSSZm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4538 $xmm16 = VSQRTSSZm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4539 ; CHECK: $xmm16 = VSQRTSSZm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4540 $xmm16 = VSQRTSSZm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4541 ; CHECK: $xmm16 = VSQRTSSZr $xmm16, $xmm1, implicit $mxcsr
4542 $xmm16 = VSQRTSSZr $xmm16, $xmm1, implicit $mxcsr
4543 ; CHECK: $xmm16 = VSQRTSSZr_Int $xmm16, $xmm1, implicit $mxcsr
4544 $xmm16 = VSQRTSSZr_Int $xmm16, $xmm1, implicit $mxcsr
4545 ; CHECK: $rdi = VCVTSD2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4546 $rdi = VCVTSD2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4547 ; CHECK: $rdi = VCVTSD2SI64Zrr_Int $xmm16, implicit $mxcsr
4548 $rdi = VCVTSD2SI64Zrr_Int $xmm16, implicit $mxcsr
4549 ; CHECK: $edi = VCVTSD2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4550 $edi = VCVTSD2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4551 ; CHECK: $edi = VCVTSD2SIZrr_Int $xmm16, implicit $mxcsr
4552 $edi = VCVTSD2SIZrr_Int $xmm16, implicit $mxcsr
4553 ; CHECK: $xmm16 = VCVTSD2SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4554 $xmm16 = VCVTSD2SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4555 ; CHECK: $xmm16 = VCVTSD2SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4556 $xmm16 = VCVTSD2SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4557 ; CHECK: $xmm16 = VCVTSD2SSZrr $xmm16, $xmm16, implicit $mxcsr
4558 $xmm16 = VCVTSD2SSZrr $xmm16, $xmm16, implicit $mxcsr
4559 ; CHECK: $xmm16 = VCVTSD2SSZrr_Int $xmm16, $xmm16, implicit $mxcsr
4560 $xmm16 = VCVTSD2SSZrr_Int $xmm16, $xmm16, implicit $mxcsr
4569 ; CHECK: $xmm16 = VCVTSI2SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4570 $xmm16 = VCVTSI2SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4571 ; CHECK: $xmm16 = VCVTSI2SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4572 $xmm16 = VCVTSI2SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4573 ; CHECK: $xmm16 = VCVTSI2SSZrr $xmm16, $edi, implicit $mxcsr
4574 $xmm16 = VCVTSI2SSZrr $xmm16, $edi, implicit $mxcsr
4575 ; CHECK: $xmm16 = VCVTSI2SSZrr_Int $xmm16, $edi, implicit $mxcsr
4576 $xmm16 = VCVTSI2SSZrr_Int $xmm16, $edi, implicit $mxcsr
4577 ; CHECK: $xmm16 = VCVTSI642SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4578 $xmm16 = VCVTSI642SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4579 ; CHECK: $xmm16 = VCVTSI642SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4580 $xmm16 = VCVTSI642SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4581 ; CHECK: $xmm16 = VCVTSI642SDZrr $xmm16, $rdi, implicit $mxcsr
4582 $xmm16 = VCVTSI642SDZrr $xmm16, $rdi, implicit $mxcsr
4583 ; CHECK: $xmm16 = VCVTSI642SDZrr_Int $xmm16, $rdi, implicit $mxcsr
4584 $xmm16 = VCVTSI642SDZrr_Int $xmm16, $rdi, implicit $mxcsr
4585 ; CHECK: $xmm16 = VCVTSI642SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4586 $xmm16 = VCVTSI642SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4587 ; CHECK: $xmm16 = VCVTSI642SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4588 $xmm16 = VCVTSI642SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4589 ; CHECK: $xmm16 = VCVTSI642SSZrr $xmm16, $rdi, implicit $mxcsr
4590 $xmm16 = VCVTSI642SSZrr $xmm16, $rdi, implicit $mxcsr
4591 ; CHECK: $xmm16 = VCVTSI642SSZrr_Int $xmm16, $rdi, implicit $mxcsr
4592 $xmm16 = VCVTSI642SSZrr_Int $xmm16, $rdi, implicit $mxcsr
4593 ; CHECK: $xmm16 = VCVTSS2SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4594 $xmm16 = VCVTSS2SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4595 ; CHECK: $xmm16 = VCVTSS2SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4596 $xmm16 = VCVTSS2SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4597 ; CHECK: $xmm16 = VCVTSS2SDZrr $xmm16, $xmm16, implicit $mxcsr
4598 $xmm16 = VCVTSS2SDZrr $xmm16, $xmm16, implicit $mxcsr
4599 ; CHECK: $xmm16 = VCVTSS2SDZrr_Int $xmm16, $xmm16, implicit $mxcsr
4600 $xmm16 = VCVTSS2SDZrr_Int $xmm16, $xmm16, implicit $mxcsr
4601 ; CHECK: $rdi = VCVTSS2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4602 $rdi = VCVTSS2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4603 ; CHECK: $rdi = VCVTSS2SI64Zrr_Int $xmm16, implicit $mxcsr
4604 $rdi = VCVTSS2SI64Zrr_Int $xmm16, implicit $mxcsr
4605 ; CHECK: $edi = VCVTSS2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4606 $edi = VCVTSS2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4607 ; CHECK: $edi = VCVTSS2SIZrr_Int $xmm16, implicit $mxcsr
4608 $edi = VCVTSS2SIZrr_Int $xmm16, implicit $mxcsr
4609 ; CHECK: $rdi = VCVTTSD2SI64rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4610 $rdi = VCVTTSD2SI64Zrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4611 ; CHECK: $rdi = VCVTTSD2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4612 $rdi = VCVTTSD2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4613 ; CHECK: $rdi = VCVTTSD2SI64Zrr $xmm16, implicit $mxcsr
4614 $rdi = VCVTTSD2SI64Zrr $xmm16, implicit $mxcsr
4615 ; CHECK: $rdi = VCVTTSD2SI64Zrr_Int $xmm16, implicit $mxcsr
4616 $rdi = VCVTTSD2SI64Zrr_Int $xmm16, implicit $mxcsr
4617 ; CHECK: $edi = VCVTTSD2SIrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4618 $edi = VCVTTSD2SIZrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4619 ; CHECK: $edi = VCVTTSD2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4620 $edi = VCVTTSD2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4621 ; CHECK: $edi = VCVTTSD2SIZrr $xmm16, implicit $mxcsr
4622 $edi = VCVTTSD2SIZrr $xmm16, implicit $mxcsr
4623 ; CHECK: $edi = VCVTTSD2SIZrr_Int $xmm16, implicit $mxcsr
4624 $edi = VCVTTSD2SIZrr_Int $xmm16, implicit $mxcsr
4625 ; CHECK: $rdi = VCVTTSS2SI64rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4626 $rdi = VCVTTSS2SI64Zrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4627 ; CHECK: $rdi = VCVTTSS2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4628 $rdi = VCVTTSS2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4629 ; CHECK: $rdi = VCVTTSS2SI64Zrr $xmm16, implicit $mxcsr
4630 $rdi = VCVTTSS2SI64Zrr $xmm16, implicit $mxcsr
4631 ; CHECK: $rdi = VCVTTSS2SI64Zrr_Int $xmm16, implicit $mxcsr
4632 $rdi = VCVTTSS2SI64Zrr_Int $xmm16, implicit $mxcsr
4633 ; CHECK: $edi = VCVTTSS2SIrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4634 $edi = VCVTTSS2SIZrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4635 ; CHECK: $edi = VCVTTSS2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4636 $edi = VCVTTSS2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4637 ; CHECK: $edi = VCVTTSS2SIZrr $xmm16, implicit $mxcsr
4638 $edi = VCVTTSS2SIZrr $xmm16, implicit $mxcsr
4639 ; CHECK: $edi = VCVTTSS2SIZrr_Int $xmm16, implicit $mxcsr
4640 $edi = VCVTTSS2SIZrr_Int $xmm16, implicit $mxcsr
4699 …_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4700 … $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4701 ; CHECK: VCOMISDZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4702 VCOMISDZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4703 …_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4704 … $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4705 ; CHECK: VCOMISSZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4706 VCOMISSZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4707 …m_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4708 … $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4709 ; CHECK: VUCOMISDZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4710 VUCOMISDZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4711 …m_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4712 … $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4713 ; CHECK: VUCOMISSZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4714 VUCOMISSZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4715 … $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4716 … $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4717 ; CHECK: VCOMISDZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4718 VCOMISDZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4719 … $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4720 … $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4721 ; CHECK: VCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4722 VCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4723 …m $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4724 … $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4725 ; CHECK: VUCOMISDZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4726 VUCOMISDZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4727 …m $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4728 … $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4729 ; CHECK: VUCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4730 VUCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4731 … CHECK: $xmm16 = VRNDSCALESDZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4732 …xmm16 = VRNDSCALESDZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4733 ; CHECK: $xmm16 = VRNDSCALESDZr $xmm16, $xmm1, 15, implicit $mxcsr
4734 $xmm16 = VRNDSCALESDZr $xmm16, $xmm1, 15, implicit $mxcsr
4735 … CHECK: $xmm16 = VRNDSCALESSZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4736 …xmm16 = VRNDSCALESSZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4737 ; CHECK: $xmm16 = VRNDSCALESSZr $xmm16, $xmm1, 15, implicit $mxcsr
4738 $xmm16 = VRNDSCALESSZr $xmm16, $xmm1, 15, implicit $mxcsr
4739 … CHECK: $xmm16 = VRNDSCALESDZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4740 …xmm16 = VRNDSCALESDZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4741 ; CHECK: $xmm16 = VRNDSCALESDZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
4742 $xmm16 = VRNDSCALESDZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
4743 … CHECK: $xmm16 = VRNDSCALESSZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4744 …xmm16 = VRNDSCALESSZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4745 ; CHECK: $xmm16 = VRNDSCALESSZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
4746 $xmm16 = VRNDSCALESSZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
4747 …; CHECK: $xmm0 = VRNDSCALESDZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4748 …$xmm0 = VRNDSCALESDZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4749 ; CHECK: $xmm0 = VRNDSCALESDZr $xmm0, $xmm1, 31, implicit $mxcsr
4750 $xmm0 = VRNDSCALESDZr $xmm0, $xmm1, 31, implicit $mxcsr
4751 …; CHECK: $xmm0 = VRNDSCALESSZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4752 …$xmm0 = VRNDSCALESSZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4753 ; CHECK: $xmm0 = VRNDSCALESSZr $xmm0, $xmm1, 31, implicit $mxcsr
4754 $xmm0 = VRNDSCALESSZr $xmm0, $xmm1, 31, implicit $mxcsr
4755 …; CHECK: $xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4756 …$xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4757 ; CHECK: $xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
4758 $xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
4759 …; CHECK: $xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4760 …$xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4761 ; CHECK: $xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
4762 $xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 31, implicit $mxcsr