Lines Matching refs:InVec

8 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
13   %shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
17 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
23   %shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
27 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
33   %shl = shl <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
37 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
42   %shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
46 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
52   %shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
56 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
62   %shl = shl <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
66 define <2 x i64> @test_sllq_1(<2 x i64> %InVec) {
71   %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
75 define <2 x i64> @test_sllq_2(<2 x i64> %InVec) {
81   %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
85 define <2 x i64> @test_sllq_3(<2 x i64> %InVec) {
91   %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
97 define <8 x i16> @test_sraw_1(<8 x i16> %InVec) {
102   %shl = ashr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
106 define <8 x i16> @test_sraw_2(<8 x i16> %InVec) {
112   %shl = ashr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
116 define <8 x i16> @test_sraw_3(<8 x i16> %InVec) {
122   %shl = ashr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
126 define <4 x i32> @test_srad_1(<4 x i32> %InVec) {
131   %shl = ashr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
135 define <4 x i32> @test_srad_2(<4 x i32> %InVec) {
141   %shl = ashr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
145 define <4 x i32> @test_srad_3(<4 x i32> %InVec) {
151   %shl = ashr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
157 define <8 x i16> @test_srlw_1(<8 x i16> %InVec) {
162   %shl = lshr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
166 define <8 x i16> @test_srlw_2(<8 x i16> %InVec) {
172   %shl = lshr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
176 define <8 x i16> @test_srlw_3(<8 x i16> %InVec) {
182   %shl = lshr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
186 define <4 x i32> @test_srld_1(<4 x i32> %InVec) {
191   %shl = lshr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
195 define <4 x i32> @test_srld_2(<4 x i32> %InVec) {
201   %shl = lshr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
205 define <4 x i32> @test_srld_3(<4 x i32> %InVec) {
211   %shl = lshr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
215 define <2 x i64> @test_srlq_1(<2 x i64> %InVec) {
220   %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
224 define <2 x i64> @test_srlq_2(<2 x i64> %InVec) {
230   %shl = lshr <2 x i64> %InVec, <i64 1, i64 1>
234 define <2 x i64> @test_srlq_3(<2 x i64> %InVec) {
240   %shl = lshr <2 x i64> %InVec, <i64 63, i64 63>