Lines Matching refs:I0
15 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
17 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
48 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
50 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
81 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
83 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
112 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
114 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
143 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
145 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
205 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
206 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
236 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
238 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
270 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
273 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
305 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
308 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4