Lines Matching refs:SHL

12 ; CHECK-NEXT:    [[SHL:%.*]] = shl i8 [[X:%.*]], [[Y:%.*]]
13 ; CHECK-NEXT:    [[R:%.*]] = icmp ult i8 [[SHL]], 4
24 ; CHECK-NEXT:    [[SHL:%.*]] = shl i16 [[X:%.*]], [[Y:%.*]]
25 ; CHECK-NEXT:    [[R:%.*]] = icmp ult i16 [[SHL]], 128
36 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
37 ; CHECK-NEXT:    [[R:%.*]] = icmp ult i32 [[SHL]], 262144
48 ; CHECK-NEXT:    [[SHL:%.*]] = shl i64 [[X:%.*]], [[Y:%.*]]
49 ; CHECK-NEXT:    [[R:%.*]] = icmp ult i64 [[SHL]], 8589934592
60 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
61 ; CHECK-NEXT:    [[R:%.*]] = icmp ugt i32 [[SHL]], 262143
74 ; CHECK-NEXT:    [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
75 ; CHECK-NEXT:    [[R:%.*]] = icmp ult <4 x i32> [[SHL]], <i32 8, i32 8, i32 8, i32 8>
86 ; CHECK-NEXT:    [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
87 ; CHECK-NEXT:    [[AND:%.*]] = and <4 x i32> [[SHL]], <i32 -8, i32 undef, i32 -8, i32 -8>
99 ; CHECK-NEXT:    [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
100 ; CHECK-NEXT:    [[AND:%.*]] = and <4 x i32> [[SHL]], <i32 -8, i32 -8, i32 -8, i32 -8>
112 ; CHECK-NEXT:    [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]]
113 ; CHECK-NEXT:    [[AND:%.*]] = and <4 x i32> [[SHL]], <i32 -8, i32 -8, i32 undef, i32 -8>
128 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
129 ; CHECK-NEXT:    [[XOR:%.*]] = xor i32 [[SHL]], [[Z:%.*]]
131 ; CHECK-NEXT:    [[R:%.*]] = icmp ult i32 [[SHL]], 8
145 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
146 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHL]], -8
163 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
164 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHL]], -8
166 ; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[SHL]], [[Z:%.*]]
186 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 12345, [[Y:%.*]]
187 ; CHECK-NEXT:    [[R:%.*]] = icmp ult i32 [[SHL]], 8
211 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
212 ; CHECK-NEXT:    [[R:%.*]] = icmp slt i32 [[SHL]], 0