Lines Matching refs:I0
18 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
20 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
51 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
53 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
84 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
86 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
115 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
117 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
146 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
148 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
208 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
209 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
239 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
241 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
273 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
276 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4
308 ; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
311 ; CHECK-NEXT: store i32 [[I0]], i32* [[D0:%.*]], align 4