Lines Matching refs:RegIdx
114 void PutInWorklist(unsigned RegIdx) { in PutInWorklist() argument
115 if (WorklistMembers.test(RegIdx)) in PutInWorklist()
117 WorklistMembers.set(RegIdx); in PutInWorklist()
118 Worklist.push_back(RegIdx); in PutInWorklist()
366 unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg); in determineInitialDefinedLanes() local
367 DefinedByCopy.set(RegIdx); in determineInitialDefinedLanes()
368 PutInWorklist(RegIdx); in determineInitialDefinedLanes()
499 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in runOnce() local
500 unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx); in runOnce()
503 VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()
510 unsigned RegIdx = Worklist.front(); in runOnce() local
512 WorklistMembers.reset(RegIdx); in runOnce()
513 VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()
514 unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx); in runOnce()
527 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in runOnce()
528 unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx); in runOnce()
529 const VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()
547 unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg); in runOnce() local
548 const VRegInfo &RegInfo = VRegInfos[RegIdx]; in runOnce()