Lines Matching refs:NewMI
720 MachineInstr *NewMI = in removeCopyByCommutingDef() local
722 if (!NewMI) in removeCopyByCommutingDef()
728 if (NewMI != DefMI) { in removeCopyByCommutingDef()
729 LIS->ReplaceMachineInstrInMaps(*DefMI, *NewMI); in removeCopyByCommutingDef()
731 MBB->insert(Pos, NewMI); in removeCopyByCommutingDef()
957 MachineInstr &NewMI = *std::prev(MII); in reMaterializeTrivialDef() local
958 NewMI.setDebugLoc(DL); in reMaterializeTrivialDef()
967 MachineOperand &DefMO = NewMI.getOperand(0); in reMaterializeTrivialDef()
999 LIS->ReplaceMachineInstrInMaps(*CopyMI, NewMI); in reMaterializeTrivialDef()
1007 for (unsigned i = NewMI.getDesc().getNumOperands(), in reMaterializeTrivialDef()
1008 e = NewMI.getNumOperands(); in reMaterializeTrivialDef()
1010 MachineOperand &MO = NewMI.getOperand(i); in reMaterializeTrivialDef()
1019 unsigned NewIdx = NewMI.getOperand(0).getSubReg(); in reMaterializeTrivialDef()
1037 NewMI.getOperand(0).setSubReg(NewIdx); in reMaterializeTrivialDef()
1053 SlotIndex CurrIdx = LIS->getInstructionIndex(NewMI); in reMaterializeTrivialDef()
1055 CurrIdx.getRegSlot(NewMI.getOperand(0).isEarlyClobber()); in reMaterializeTrivialDef()
1068 } else if (NewMI.getOperand(0).getReg() != CopyDstReg) { in reMaterializeTrivialDef()
1073 NewMI.getOperand(0).setIsDead(true); in reMaterializeTrivialDef()
1074 NewMI.addOperand(MachineOperand::CreateReg( in reMaterializeTrivialDef()
1092 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI); in reMaterializeTrivialDef()
1093 for (MCRegUnitIterator Units(NewMI.getOperand(0).getReg(), TRI); in reMaterializeTrivialDef()
1099 if (NewMI.getOperand(0).getSubReg()) in reMaterializeTrivialDef()
1100 NewMI.getOperand(0).setIsUndef(); in reMaterializeTrivialDef()
1104 NewMI.addOperand(MO); in reMaterializeTrivialDef()
1106 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI); in reMaterializeTrivialDef()
1114 DEBUG(dbgs() << "Remat: " << NewMI); in reMaterializeTrivialDef()