Lines Matching refs:SignBit
1359 uint8_t SignBit; member
1377 State.SignBit = NumBits - 1; in getSignAsIntValue()
1414 State.SignBit = 7; in getSignAsIntValue()
1444 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN() local
1453 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1467 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; in ExpandFCOPYSIGN()
1468 if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) { in ExpandFCOPYSIGN()
1471 SignBit = DAG.getNode(ISD::SRL, DL, IntVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1474 SignBit = DAG.getNode(ISD::SHL, DL, IntVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1476 SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit); in ExpandFCOPYSIGN()
1477 } else if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) { in ExpandFCOPYSIGN()
1478 SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit); in ExpandFCOPYSIGN()
1481 SignBit = DAG.getNode(ISD::SRL, DL, MagVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1484 SignBit = DAG.getNode(ISD::SHL, DL, MagVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1489 SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit); in ExpandFCOPYSIGN()
2290 SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32); in ExpandLegalINT_TO_FP() local
2291 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); in ExpandLegalINT_TO_FP()