Lines Matching refs:SUnit
125 std::vector<SUnit*> PendingQueue;
144 std::unique_ptr<SUnit*[]> LiveRegDefs;
145 std::unique_ptr<SUnit*[]> LiveRegGens;
149 SmallVector<SUnit*, 4> Interferences;
150 typedef DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMapT;
159 DenseMap<SUnit*, SUnit*> CallSeqEndForStart;
186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable()
192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle()
199 void AddPred(SUnit *SU, const SDep &D) { in AddPred()
207 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred()
213 bool isReady(SUnit *SU) { in isReady()
218 void ReleasePred(SUnit *SU, const SDep *PredEdge);
219 void ReleasePredecessors(SUnit *SU);
222 void AdvancePastStalls(SUnit *SU);
223 void EmitNode(SUnit *SU);
224 void ScheduleNodeBottomUp(SUnit*);
226 void UnscheduleNodeBottomUp(SUnit*);
228 void BacktrackBottomUp(SUnit*, SUnit*);
229 SUnit *CopyAndMoveSuccessors(SUnit*);
230 void InsertCopiesAndMoveSuccs(SUnit*, unsigned,
233 SmallVectorImpl<SUnit*>&);
234 bool DelayForLiveRegsBottomUp(SUnit*, SmallVectorImpl<unsigned>&);
238 SUnit *PickNodeToScheduleBottomUp();
243 SUnit *CreateNewSUnit(SDNode *N) { in CreateNewSUnit()
245 SUnit *NewNode = newSUnit(N); in CreateNewSUnit()
254 SUnit *CreateClone(SUnit *N) { in CreateClone()
256 SUnit *NewNode = Clone(N); in CreateClone()
331 LiveRegDefs.reset(new SUnit*[TRI->getNumRegs() + 1]()); in Schedule()
332 LiveRegGens.reset(new SUnit*[TRI->getNumRegs() + 1]()); in Schedule()
339 DEBUG(for (SUnit &SU : SUnits) in Schedule()
365 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { in ReleasePred()
366 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
525 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) { in ReleasePredecessors()
527 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in ReleasePredecessors()
535 SUnit *RegDef = LiveRegDefs[I->getReg()]; (void)RegDef; in ReleasePredecessors()
558 SUnit *Def = &SUnits[N->getNodeId()]; in ReleasePredecessors()
622 void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) { in AdvancePastStalls()
664 void ScheduleDAGRRList::EmitNode(SUnit *SU) { in EmitNode()
701 static void resetVRegCycle(SUnit *SU);
706 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) { in ScheduleNodeBottomUp()
740 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in ScheduleNodeBottomUp()
792 SUnit *PredSU = PredEdge->getSUnit(); in CapturePred()
805 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { in UnscheduleNodeBottomUp()
809 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in UnscheduleNodeBottomUp()
900 std::vector<SUnit*>::const_iterator I = (Sequence.end() - LookAhead); in RestoreHazardCheckerBottomUp()
902 for (std::vector<SUnit*>::const_iterator E = Sequence.end(); I != E; ++I) { in RestoreHazardCheckerBottomUp()
903 SUnit *SU = *I; in RestoreHazardCheckerBottomUp()
913 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) { in BacktrackBottomUp()
914 SUnit *OldSU = Sequence.back(); in BacktrackBottomUp()
935 static bool isOperandOf(const SUnit *SU, SDNode *N) { in isOperandOf()
946 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { in CopyAndMoveSuccessors()
954 SUnit *NewSU; in CopyAndMoveSuccessors()
995 SUnit *LoadSU; in CopyAndMoveSuccessors()
1007 SUnit *NewSU = CreateNewSUnit(N); in CopyAndMoveSuccessors()
1061 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
1072 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
1110 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; in CopyAndMoveSuccessors()
1114 SUnit *SuccSU = Succ.getSUnit(); in CopyAndMoveSuccessors()
1135 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, in InsertCopiesAndMoveSuccs()
1138 SmallVectorImpl<SUnit*> &Copies) { in InsertCopiesAndMoveSuccs()
1139 SUnit *CopyFromSU = CreateNewSUnit(nullptr); in InsertCopiesAndMoveSuccs()
1143 SUnit *CopyToSU = CreateNewSUnit(nullptr); in InsertCopiesAndMoveSuccs()
1149 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps; in InsertCopiesAndMoveSuccs()
1153 SUnit *SuccSU = Succ.getSUnit(); in InsertCopiesAndMoveSuccs()
1210 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg, in CheckForLiveRegDef()
1211 SUnit **LiveRegDefs, in CheckForLiveRegDef()
1232 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, in CheckForLiveRegDefMasked()
1233 ArrayRef<SUnit*> LiveRegDefs, in CheckForLiveRegDefMasked()
1259 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) { in DelayForLiveRegsBottomUp()
1268 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in DelayForLiveRegsBottomUp()
1338 SUnit *SU = Interferences[i-1]; in releaseInterferences()
1364 SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() { in PickNodeToScheduleBottomUp()
1365 SUnit *CurSU = AvailableQueue->empty() ? nullptr : AvailableQueue->pop(); in PickNodeToScheduleBottomUp()
1393 for (SUnit *TrySU : Interferences) { in PickNodeToScheduleBottomUp()
1398 SUnit *BtSU = nullptr; in PickNodeToScheduleBottomUp()
1441 SUnit *TrySU = Interferences[0]; in PickNodeToScheduleBottomUp()
1445 SUnit *LRDef = LiveRegDefs[Reg]; in PickNodeToScheduleBottomUp()
1458 SUnit *NewDef = nullptr; in PickNodeToScheduleBottomUp()
1466 SmallVector<SUnit*, 2> Copies; in PickNodeToScheduleBottomUp()
1493 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()]; in ListScheduleBottomUp()
1508 SUnit *SU = PickNodeToScheduleBottomUp(); in ListScheduleBottomUp()
1539 struct queue_sort : public std::binary_function<SUnit*, SUnit*, bool> {
1540 bool isReady(SUnit* SU, unsigned CurCycle) const { return true; } in isReady()
1549 bool operator()(SUnit* left, SUnit* right) const { in operator ()()
1568 bool operator()(SUnit* left, SUnit* right) const;
1582 bool operator()(SUnit* left, SUnit* right) const;
1596 bool isReady(SUnit *SU, unsigned CurCycle) const;
1598 bool operator()(SUnit* left, SUnit* right) const;
1613 bool isReady(SUnit *SU, unsigned CurCycle) const;
1615 bool operator()(SUnit* left, SUnit* right) const;
1620 std::vector<SUnit*> Queue;
1626 std::vector<SUnit> *SUnits;
1676 void initNodes(std::vector<SUnit> &sunits) override;
1678 void addNode(const SUnit *SU) override;
1680 void updateNode(const SUnit *SU) override;
1688 unsigned getNodePriority(const SUnit *SU) const;
1690 unsigned getNodeOrdering(const SUnit *SU) const { in getNodeOrdering()
1698 void push(SUnit *U) override { in push()
1704 void remove(SUnit *SU) override { in remove()
1707 std::vector<SUnit *>::iterator I = std::find(Queue.begin(), Queue.end(), in remove()
1719 bool HighRegPressure(const SUnit *SU) const;
1721 bool MayReduceRegPressure(SUnit *SU) const;
1723 int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const;
1725 void scheduledNode(SUnit *SU) override;
1727 void unscheduledNode(SUnit *SU) override;
1730 bool canClobber(const SUnit *SU, const SUnit *Op);
1737 static SUnit *popFromQueueImpl(std::vector<SUnit*> &Q, SF &Picker) { in popFromQueueImpl()
1738 std::vector<SUnit *>::iterator Best = Q.begin(); in popFromQueueImpl()
1739 for (std::vector<SUnit *>::iterator I = std::next(Q.begin()), in popFromQueueImpl()
1743 SUnit *V = *Best; in popFromQueueImpl()
1751 SUnit *popFromQueue(std::vector<SUnit*> &Q, SF &Picker, ScheduleDAG *DAG) { in popFromQueue()
1779 bool isReady(SUnit *U) const override { in isReady()
1783 SUnit *pop() override { in pop()
1786 SUnit *V = popFromQueue(Queue, Picker, scheduleDAG); in pop()
1794 std::vector<SUnit*> DumpQueue = Queue; in dump()
1797 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); in dump()
1828 static int checkSpecialNodes(const SUnit *left, const SUnit *right) { in checkSpecialNodes()
1839 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { in CalcNodeSethiUllmanNumber()
1847 SUnit *PredSU = Pred.getSUnit(); in CalcNodeSethiUllmanNumber()
1869 for (const SUnit &SU : *SUnits) in CalculateSethiUllmanNumbers()
1873 void RegReductionPQBase::addNode(const SUnit *SU) { in addNode()
1880 void RegReductionPQBase::updateNode(const SUnit *SU) { in updateNode()
1887 unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const { in getNodePriority()
1942 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const { in HighRegPressure()
1949 SUnit *PredSU = Pred.getSUnit(); in HighRegPressure()
1967 bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const { in MayReduceRegPressure()
1992 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const { in RegPressureDiff()
1998 SUnit *PredSU = Pred.getSUnit(); in RegPressureDiff()
2031 void RegReductionPQBase::scheduledNode(SUnit *SU) { in scheduledNode()
2041 SUnit *PredSU = Pred.getSUnit(); in scheduledNode()
2099 void RegReductionPQBase::unscheduledNode(SUnit *SU) { in unscheduledNode()
2122 SUnit *PredSU = Pred.getSUnit(); in unscheduledNode()
2185 static unsigned closestSucc(const SUnit *SU) { in closestSucc()
2203 static unsigned calcMaxScratches(const SUnit *SU) { in calcMaxScratches()
2214 static bool hasOnlyLiveInOpers(const SUnit *SU) { in hasOnlyLiveInOpers()
2218 const SUnit *PredSU = Pred.getSUnit(); in hasOnlyLiveInOpers()
2236 static bool hasOnlyLiveOutUses(const SUnit *SU) { in hasOnlyLiveOutUses()
2240 const SUnit *SuccSU = Succ.getSUnit(); in hasOnlyLiveOutUses()
2264 static void initVRegCycle(SUnit *SU) { in initVRegCycle()
2283 static void resetVRegCycle(SUnit *SU) { in resetVRegCycle()
2289 SUnit *PredSU = Pred.getSUnit(); in resetVRegCycle()
2300 static bool hasVRegCycleUse(const SUnit *SU) { in hasVRegCycleUse()
2319 static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) { in BUHasStall()
2329 static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref, in BUCompareLatency()
2380 static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) { in BURRSort()
2484 bool bu_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2492 bool src_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2511 bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { in isReady()
2526 bool hybrid_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2558 bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { in isReady()
2568 static bool canEnableCoalescing(SUnit *SU) { in canEnableCoalescing()
2592 bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const { in operator ()()
2651 void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) { in initNodes()
2664 for (SUnit &SU : sunits) in initNodes()
2672 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) { in canClobber()
2693 static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU, in canClobberReachingPhysRegUse()
2704 SUnit *SuccSU = Succ.getSUnit(); in canClobberReachingPhysRegUse()
2729 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU, in canClobberPhysRegDefs()
2799 for (SUnit &SU : *SUnits) { in PrescheduleNodesWithMultipleUses()
2817 SUnit *PredSU = nullptr; in PrescheduleNodesWithMultipleUses()
2842 SUnit *PredSuccSU = PredSucc.getSUnit(); in PrescheduleNodesWithMultipleUses()
2865 SUnit *SuccSU = Edge.getSUnit(); in PrescheduleNodesWithMultipleUses()
2887 for (SUnit &SU : *SUnits) { in AddPseudoTwoAddrDeps()
2906 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()]; in AddPseudoTwoAddrDeps()
2912 SUnit *SuccSU = Succ.getSUnit(); in AddPseudoTwoAddrDeps()