Lines Matching refs:ResultReg
323 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca() local
325 ResultReg) in fastMaterializeAlloca()
329 return ResultReg; in fastMaterializeAlloca()
346 unsigned ResultReg = createResultReg(RC); in materializeInt() local
348 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
349 return ResultReg; in materializeInt()
383 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
385 TII.get(TargetOpcode::COPY), ResultReg) in materializeFP()
388 return ResultReg; in materializeFP()
403 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
404 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in materializeFP()
407 return ResultReg; in materializeFP()
427 unsigned ResultReg; in materializeGV() local
435 ResultReg = createResultReg(&AArch64::GPR64RegClass); in materializeGV()
437 ResultReg) in materializeGV()
447 ResultReg = createResultReg(&AArch64::GPR64spRegClass); in materializeGV()
449 ResultReg) in materializeGV()
454 return ResultReg; in materializeGV()
977 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in simplifyAddress() local
979 ResultReg) in simplifyAddress()
984 Addr.setReg(ResultReg); in simplifyAddress()
988 unsigned ResultReg = 0; in simplifyAddress() local
992 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(), in simplifyAddress()
997 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(), in simplifyAddress()
1003 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1007 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1011 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(), in simplifyAddress()
1014 if (!ResultReg) in simplifyAddress()
1017 Addr.setReg(ResultReg); in simplifyAddress()
1026 unsigned ResultReg; in simplifyAddress() local
1029 ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), /*IsKill=*/false, Offset); in simplifyAddress()
1031 ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset); in simplifyAddress()
1033 if (!ResultReg) in simplifyAddress()
1035 Addr.setReg(ResultReg); in simplifyAddress()
1133 unsigned ResultReg = 0; in emitAddSub() local
1137 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm, in emitAddSub()
1140 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags, in emitAddSub()
1144 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags, in emitAddSub()
1147 if (ResultReg) in emitAddSub()
1148 return ResultReg; in emitAddSub()
1188 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1191 if (ResultReg) in emitAddSub()
1192 return ResultReg; in emitAddSub()
1213 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1216 if (ResultReg) in emitAddSub()
1217 return ResultReg; in emitAddSub()
1254 unsigned ResultReg; in emitAddSub_rr() local
1256 ResultReg = createResultReg(RC); in emitAddSub_rr()
1258 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_rr()
1263 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in emitAddSub_rr()
1266 return ResultReg; in emitAddSub_rr()
1299 unsigned ResultReg; in emitAddSub_ri() local
1301 ResultReg = createResultReg(RC); in emitAddSub_ri()
1303 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_ri()
1307 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in emitAddSub_ri()
1311 return ResultReg; in emitAddSub_ri()
1339 unsigned ResultReg; in emitAddSub_rs() local
1341 ResultReg = createResultReg(RC); in emitAddSub_rs()
1343 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_rs()
1348 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in emitAddSub_rs()
1352 return ResultReg; in emitAddSub_rs()
1382 unsigned ResultReg; in emitAddSub_rx() local
1384 ResultReg = createResultReg(RC); in emitAddSub_rx()
1386 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_rx()
1391 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in emitAddSub_rx()
1395 return ResultReg; in emitAddSub_rx()
1480 unsigned ResultReg; in emitAdd_ri_() local
1482 ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm); in emitAdd_ri_()
1484 ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm); in emitAdd_ri_()
1486 if (ResultReg) in emitAdd_ri_()
1487 return ResultReg; in emitAdd_ri_()
1493 ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true); in emitAdd_ri_()
1494 return ResultReg; in emitAdd_ri_()
1542 unsigned ResultReg = 0; in emitLogicalOp() local
1545 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm); in emitLogicalOp()
1547 if (ResultReg) in emitLogicalOp()
1548 return ResultReg; in emitLogicalOp()
1567 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg, in emitLogicalOp()
1569 if (ResultReg) in emitLogicalOp()
1570 return ResultReg; in emitLogicalOp()
1583 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg, in emitLogicalOp()
1585 if (ResultReg) in emitLogicalOp()
1586 return ResultReg; in emitLogicalOp()
1596 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill); in emitLogicalOp()
1599 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLogicalOp()
1601 return ResultReg; in emitLogicalOp()
1640 unsigned ResultReg = in emitLogicalOp_ri() local
1645 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLogicalOp_ri()
1647 return ResultReg; in emitLogicalOp_ri()
1683 unsigned ResultReg = in emitLogicalOp_rs() local
1688 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLogicalOp_rs()
1690 return ResultReg; in emitLogicalOp_rs()
1809 unsigned ResultReg = createResultReg(RC); in emitLoad() local
1811 TII.get(Opc), ResultReg); in emitLoad()
1816 unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1); in emitLoad()
1818 ResultReg = ANDReg; in emitLoad()
1828 .addReg(ResultReg, getKillRegState(true)) in emitLoad()
1830 ResultReg = Reg64; in emitLoad()
1832 return ResultReg; in emitLoad()
1843 unsigned ResultReg; in selectAddSub() local
1848 ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1)); in selectAddSub()
1851 ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1)); in selectAddSub()
1854 if (!ResultReg) in selectAddSub()
1857 updateValueMap(I, ResultReg); in selectAddSub()
1869 unsigned ResultReg; in selectLogicalOp() local
1874 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1877 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1880 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1883 if (!ResultReg) in selectLogicalOp()
1886 updateValueMap(I, ResultReg); in selectLogicalOp()
1938 unsigned ResultReg = in selectLoad() local
1940 if (!ResultReg) in selectLoad()
1966 ResultReg = std::prev(FuncInfo.InsertPt)->getOperand(0).getReg(); in selectLoad()
1968 ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg, in selectLoad()
1972 updateValueMap(I, ResultReg); in selectLoad()
1992 updateValueMap(IntExtVal, ResultReg); in selectLoad()
1996 updateValueMap(I, ResultReg); in selectLoad()
2446 unsigned ResultReg = 0; in selectCmp() local
2451 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2453 TII.get(TargetOpcode::COPY), ResultReg) in selectCmp()
2457 ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1); in selectCmp()
2461 if (ResultReg) { in selectCmp()
2462 updateValueMap(I, ResultReg); in selectCmp()
2470 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2498 ResultReg) in selectCmp()
2503 updateValueMap(I, ResultReg); in selectCmp()
2512 ResultReg) in selectCmp()
2517 updateValueMap(I, ResultReg); in selectCmp()
2572 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, in optimizeSelect() local
2574 updateValueMap(SI, ResultReg); in optimizeSelect()
2702 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect() local
2704 updateValueMap(I, ResultReg); in selectSelect()
2717 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass); in selectFPExt() local
2719 ResultReg).addReg(Op); in selectFPExt()
2720 updateValueMap(I, ResultReg); in selectFPExt()
2733 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass); in selectFPTrunc() local
2735 ResultReg).addReg(Op); in selectFPTrunc()
2736 updateValueMap(I, ResultReg); in selectFPTrunc()
2766 unsigned ResultReg = createResultReg( in selectFPToInt() local
2768 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in selectFPToInt()
2770 updateValueMap(I, ResultReg); in selectFPToInt()
2814 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, in selectIntToFP() local
2816 updateValueMap(I, ResultReg); in selectIntToFP()
2922 unsigned ResultReg = createResultReg(RC); in fastLowerArguments() local
2924 TII.get(TargetOpcode::COPY), ResultReg) in fastLowerArguments()
2926 updateValueMap(&Arg, ResultReg); in fastLowerArguments()
3047 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall() local
3049 TII.get(TargetOpcode::COPY), ResultReg) in finishCall()
3053 CLI.ResultReg = ResultReg; in finishCall()
3220 unsigned ResultReg = emitLoad(VT, VT, Src); in tryEmitSmallMemCpy() local
3221 if (!ResultReg) in tryEmitSmallMemCpy()
3224 if (!emitStore(VT, ResultReg, Dest)) in tryEmitSmallMemCpy()
3461 updateValueMap(II, CLI.ResultReg); in fastLowerIntrinsicCall()
3484 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall() local
3485 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastLowerIntrinsicCall()
3487 updateValueMap(II, ResultReg); in fastLowerIntrinsicCall()
3507 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill); in fastLowerIntrinsicCall() local
3508 if (!ResultReg) in fastLowerIntrinsicCall()
3511 updateValueMap(II, ResultReg); in fastLowerIntrinsicCall()
3801 unsigned ResultReg; in selectTrunc() local
3822 ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask); in selectTrunc()
3823 assert(ResultReg && "Unexpected AND instruction emission failure."); in selectTrunc()
3825 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectTrunc()
3827 TII.get(TargetOpcode::COPY), ResultReg) in selectTrunc()
3831 updateValueMap(I, ResultReg); in selectTrunc()
3844 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1); in emiti1Ext() local
3845 assert(ResultReg && "Unexpected AND instruction emission failure."); in emiti1Ext()
3853 .addReg(ResultReg) in emiti1Ext()
3855 ResultReg = Reg64; in emiti1Ext()
3857 return ResultReg; in emiti1Ext()
3927 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSL_rr() local
3930 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLSL_rr()
3931 return ResultReg; in emitLSL_rr()
3955 unsigned ResultReg = createResultReg(RC); in emitLSL_ri() local
3957 TII.get(TargetOpcode::COPY), ResultReg) in emitLSL_ri()
3959 return ResultReg; in emitLSL_ri()
4034 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSR_rr() local
4037 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitLSR_rr()
4038 return ResultReg; in emitLSR_rr()
4062 unsigned ResultReg = createResultReg(RC); in emitLSR_ri() local
4064 TII.get(TargetOpcode::COPY), ResultReg) in emitLSR_ri()
4066 return ResultReg; in emitLSR_ri()
4155 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitASR_rr() local
4158 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); in emitASR_rr()
4159 return ResultReg; in emitASR_rr()
4183 unsigned ResultReg = createResultReg(RC); in emitASR_ri() local
4185 TII.get(TargetOpcode::COPY), ResultReg) in emitASR_ri()
4187 return ResultReg; in emitASR_ri()
4431 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass); in selectIntExt() local
4433 TII.get(AArch64::SUBREG_TO_REG), ResultReg) in selectIntExt()
4437 SrcReg = ResultReg; in selectIntExt()
4452 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt() local
4453 if (!ResultReg) in selectIntExt()
4456 updateValueMap(I, ResultReg); in selectIntExt()
4499 unsigned ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true, in selectRem() local
4502 updateValueMap(I, ResultReg); in selectRem()
4551 unsigned ResultReg = in selectMul() local
4554 if (ResultReg) { in selectMul()
4555 updateValueMap(I, ResultReg); in selectMul()
4570 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul() local
4572 if (!ResultReg) in selectMul()
4575 updateValueMap(I, ResultReg); in selectMul()
4588 unsigned ResultReg = 0; in selectShift() local
4621 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4624 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4627 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4630 if (!ResultReg) in selectShift()
4633 updateValueMap(I, ResultReg); in selectShift()
4647 unsigned ResultReg = 0; in selectShift() local
4651 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4654 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4657 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4661 if (!ResultReg) in selectShift()
4664 updateValueMap(I, ResultReg); in selectShift()
4700 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill); in selectBitCast() local
4702 if (!ResultReg) in selectBitCast()
4705 updateValueMap(I, ResultReg); in selectBitCast()
4743 updateValueMap(I, CLI.ResultReg); in selectFRem()
4767 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv() local
4768 if (!ResultReg) in selectSDiv()
4770 updateValueMap(I, ResultReg); in selectSDiv()
4801 unsigned ResultReg; in selectSDiv() local
4803 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true, in selectSDiv()
4806 ResultReg = emitASR_ri(VT, VT, SelectReg, /*IsKill=*/true, Lg2); in selectSDiv()
4808 if (!ResultReg) in selectSDiv()
4811 updateValueMap(I, ResultReg); in selectSDiv()