Lines Matching refs:RetVT
153 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
158 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
161 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
164 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
167 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
172 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
181 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
182 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
183 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
190 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
194 unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
197 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
199 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
203 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
205 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
207 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
210 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
211 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
213 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
215 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
217 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
219 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
221 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
223 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
225 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
227 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
239 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
1081 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS, in emitAddSub() argument
1086 switch (RetVT.SimpleTy) { in emitAddSub()
1104 MVT SrcVT = RetVT; in emitAddSub()
1105 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32); in emitAddSub()
1131 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1137 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm, in emitAddSub()
1140 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags, in emitAddSub()
1144 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags, in emitAddSub()
1160 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1168 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill, in emitAddSub()
1188 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1213 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1229 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1231 return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill, in emitAddSub()
1235 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rr() argument
1241 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rr()
1250 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rr()
1269 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_ri() argument
1274 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_ri()
1292 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_ri()
1314 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rs() argument
1322 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rs()
1326 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs()
1335 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rs()
1355 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rx() argument
1363 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rx()
1375 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rx()
1420 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, in emitICmp() argument
1422 return emitSub(RetVT, LHS, RHS, /*SetFlags=*/true, /*WantResult=*/false, in emitICmp()
1426 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, in emitICmp_ri() argument
1428 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm, in emitICmp_ri()
1432 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) { in emitFCmp() argument
1433 if (RetVT != MVT::f32 && RetVT != MVT::f64) in emitFCmp()
1449 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri; in emitFCmp()
1460 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr; in emitFCmp()
1467 unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS, in emitAdd() argument
1469 return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult, in emitAdd()
1497 unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS, in emitSub() argument
1499 return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult, in emitSub()
1503 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg, in emitSubs_rr() argument
1506 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg, in emitSubs_rr()
1510 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg, in emitSubs_rs() argument
1515 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg, in emitSubs_rs()
1520 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, in emitLogicalOp() argument
1545 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm); in emitLogicalOp()
1567 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg, in emitLogicalOp()
1583 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg, in emitLogicalOp()
1595 MVT VT = std::max(MVT::i32, RetVT.SimpleTy); in emitLogicalOp()
1597 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) { in emitLogicalOp()
1598 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp()
1604 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, in emitLogicalOp_ri() argument
1617 switch (RetVT.SimpleTy) { in emitLogicalOp_ri()
1643 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) { in emitLogicalOp_ri()
1644 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp_ri()
1650 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, in emitLogicalOp_rs() argument
1663 if (ShiftImm >= RetVT.getSizeInBits()) in emitLogicalOp_rs()
1668 switch (RetVT.SimpleTy) { in emitLogicalOp_rs()
1686 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) { in emitLogicalOp_rs()
1687 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp_rs()
1693 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, in emitAnd_ri() argument
1695 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm); in emitAnd_ri()
1698 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr, in emitLoad() argument
1774 bool IsRet64Bit = RetVT == MVT::i64; in emitLoad()
1823 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) { in emitLoad()
1921 MVT RetVT = VT; in selectLoad() local
1925 if (isTypeSupported(ZE->getType(), RetVT)) in selectLoad()
1928 RetVT = VT; in selectLoad()
1930 if (isTypeSupported(SE->getType(), RetVT)) in selectLoad()
1933 RetVT = VT; in selectLoad()
1939 emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I)); in selectLoad()
1962 if (RetVT == MVT::i64 && VT <= MVT::i32) { in selectLoad()
3021 bool AArch64FastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT, in finishCall() argument
3031 if (RetVT != MVT::isVoid) { in finishCall()
3034 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC)); in finishCall()
3088 MVT RetVT; in fastLowerCall() local
3090 RetVT = MVT::isVoid; in fastLowerCall()
3091 else if (!isTypeLegal(CLI.RetTy, RetVT)) in fastLowerCall()
3177 return finishCall(CLI, RetVT, NumBytes); in fastLowerCall()
3252 MVT RetVT; in foldXALUIntrinsic() local
3256 if (!isTypeLegal(RetTy, RetVT)) in foldXALUIntrinsic()
3259 if (RetVT != MVT::i32 && RetVT != MVT::i64) in foldXALUIntrinsic()
3416 MVT RetVT; in fastLowerIntrinsicCall() local
3417 if (!isTypeLegal(II->getType(), RetVT)) in fastLowerIntrinsicCall()
3420 if (RetVT != MVT::f32 && RetVT != MVT::f64) in fastLowerIntrinsicCall()
3429 bool Is64Bit = RetVT == MVT::f64; in fastLowerIntrinsicCall()
3868 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitMul_rr() argument
3871 switch (RetVT.SimpleTy) { in emitMul_rr()
3876 RetVT = MVT::i32; in emitMul_rr()
3883 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitMul_rr()
3888 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitSMULL_rr() argument
3890 if (RetVT != MVT::i64) in emitSMULL_rr()
3898 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitUMULL_rr() argument
3900 if (RetVT != MVT::i64) in emitUMULL_rr()
3908 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, in emitLSL_rr() argument
3913 switch (RetVT.SimpleTy) { in emitLSL_rr()
3922 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSL_rr()
3934 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSL_ri() argument
3937 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSL_ri()
3942 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitLSL_ri()
3943 RetVT == MVT::i64) && "Unexpected return value type."); in emitLSL_ri()
3945 bool Is64Bit = (RetVT == MVT::i64); in emitLSL_ri()
3947 unsigned DstBits = RetVT.getSizeInBits(); in emitLSL_ri()
3954 if (RetVT == SrcVT) { in emitLSL_ri()
3961 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSL_ri()
4001 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSL_ri()
4014 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, in emitLSR_rr() argument
4019 switch (RetVT.SimpleTy) { in emitLSR_rr()
4028 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSR_rr()
4041 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSR_ri() argument
4044 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSR_ri()
4049 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitLSR_ri()
4050 RetVT == MVT::i64) && "Unexpected return value type."); in emitLSR_ri()
4052 bool Is64Bit = (RetVT == MVT::i64); in emitLSR_ri()
4054 unsigned DstBits = RetVT.getSizeInBits(); in emitLSR_ri()
4061 if (RetVT == SrcVT) { in emitLSR_ri()
4068 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4101 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitLSR_ri()
4106 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4110 SrcVT = RetVT; in emitLSR_ri()
4122 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSR_ri()
4135 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, in emitASR_rr() argument
4140 switch (RetVT.SimpleTy) { in emitASR_rr()
4149 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitASR_rr()
4151 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false); in emitASR_rr()
4162 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitASR_ri() argument
4165 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitASR_ri()
4170 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitASR_ri()
4171 RetVT == MVT::i64) && "Unexpected return value type."); in emitASR_ri()
4173 bool Is64Bit = (RetVT == MVT::i64); in emitASR_ri()
4175 unsigned DstBits = RetVT.getSizeInBits(); in emitASR_ri()
4182 if (RetVT == SrcVT) { in emitASR_ri()
4189 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitASR_ri()
4222 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitASR_ri()
4231 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitASR_ri()
4353 bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT, in optimizeIntExtLoad() argument
4382 if (RetVT != MVT::i64 || SrcVT > MVT::i32) { in optimizeIntExtLoad()
4409 MVT RetVT; in selectIntExt() local
4411 if (!isTypeSupported(I->getType(), RetVT)) in selectIntExt()
4418 if (optimizeIntExtLoad(I, RetVT, SrcVT)) in selectIntExt()
4430 if (RetVT == MVT::i64 && SrcVT != MVT::i64) { in selectIntExt()
4452 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt()
4580 MVT RetVT; in selectShift() local
4581 if (!isTypeSupported(I->getType(), RetVT, /*IsVectorAllowed=*/true)) in selectShift()
4584 if (RetVT.isVector()) in selectShift()
4590 MVT SrcVT = RetVT; in selectShift()
4621 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4624 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4627 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4651 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4654 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4657 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4669 MVT RetVT, SrcVT; in selectBitCast() local
4673 if (!isTypeLegal(I->getType(), RetVT)) in selectBitCast()
4677 if (RetVT == MVT::f32 && SrcVT == MVT::i32) in selectBitCast()
4679 else if (RetVT == MVT::f64 && SrcVT == MVT::i64) in selectBitCast()
4681 else if (RetVT == MVT::i32 && SrcVT == MVT::f32) in selectBitCast()
4683 else if (RetVT == MVT::i64 && SrcVT == MVT::f64) in selectBitCast()
4689 switch (RetVT.SimpleTy) { in selectBitCast()
4710 MVT RetVT; in selectFRem() local
4711 if (!isTypeLegal(I->getType(), RetVT)) in selectFRem()
4715 switch (RetVT.SimpleTy) { in selectFRem()