Lines Matching refs:SrcVT
153 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
188 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
219 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
223 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
227 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1104 MVT SrcVT = RetVT; in emitAddSub() local
1131 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1229 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
2750 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); in selectFPToInt() local
2751 if (SrcVT == MVT::f128 || SrcVT == MVT::f16) in selectFPToInt()
2755 if (SrcVT == MVT::f64) { in selectFPToInt()
2790 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); in selectIntToFP() local
2793 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) { in selectIntToFP()
2795 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed); in selectIntToFP()
2802 if (SrcVT == MVT::i64) { in selectIntToFP()
2962 MVT SrcVT = ArgVT; in processCallArgs() local
2963 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
2972 MVT SrcVT = ArgVT; in processCallArgs() local
2973 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
3781 MVT SrcVT = SrcEVT.getSimpleVT(); in selectTrunc() local
3784 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 && in selectTrunc()
3785 SrcVT != MVT::i8) in selectTrunc()
3802 if (SrcVT == MVT::i64) { in selectTrunc()
3934 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSL_ri() argument
3937 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSL_ri()
3939 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSL_ri()
3940 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitLSL_ri()
3948 unsigned SrcBits = SrcVT.getSizeInBits(); in emitLSL_ri()
3954 if (RetVT == SrcVT) { in emitLSL_ri()
3961 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSL_ri()
4001 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSL_ri()
4041 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSR_ri() argument
4044 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSR_ri()
4046 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSR_ri()
4047 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitLSR_ri()
4055 unsigned SrcBits = SrcVT.getSizeInBits(); in emitLSR_ri()
4061 if (RetVT == SrcVT) { in emitLSR_ri()
4068 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4106 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4110 SrcVT = RetVT; in emitLSR_ri()
4111 SrcBits = SrcVT.getSizeInBits(); in emitLSR_ri()
4122 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSR_ri()
4162 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitASR_ri() argument
4165 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitASR_ri()
4167 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitASR_ri()
4168 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitASR_ri()
4176 unsigned SrcBits = SrcVT.getSizeInBits(); in emitASR_ri()
4182 if (RetVT == SrcVT) { in emitASR_ri()
4189 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitASR_ri()
4231 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitASR_ri()
4244 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt() argument
4254 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && in emitIntExt()
4255 (SrcVT != MVT::i16) && (SrcVT != MVT::i32))) in emitIntExt()
4261 switch (SrcVT.SimpleTy) { in emitIntExt()
4354 MVT SrcVT) { in optimizeIntExtLoad() argument
4382 if (RetVT != MVT::i64 || SrcVT > MVT::i32) { in optimizeIntExtLoad()
4410 MVT SrcVT; in selectIntExt() local
4414 if (!isTypeSupported(I->getOperand(0)->getType(), SrcVT)) in selectIntExt()
4418 if (optimizeIntExtLoad(I, RetVT, SrcVT)) in selectIntExt()
4430 if (RetVT == MVT::i64 && SrcVT != MVT::i64) { in selectIntExt()
4452 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt()
4524 MVT SrcVT = VT; in selectMul() local
4530 SrcVT = VT; in selectMul()
4539 SrcVT = VT; in selectMul()
4552 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
4590 MVT SrcVT = RetVT; in selectShift() local
4597 SrcVT = TmpVT; in selectShift()
4606 SrcVT = TmpVT; in selectShift()
4621 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4624 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4627 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4669 MVT RetVT, SrcVT; in selectBitCast() local
4671 if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT)) in selectBitCast()
4677 if (RetVT == MVT::f32 && SrcVT == MVT::i32) in selectBitCast()
4679 else if (RetVT == MVT::f64 && SrcVT == MVT::i64) in selectBitCast()
4681 else if (RetVT == MVT::i32 && SrcVT == MVT::f32) in selectBitCast()
4683 else if (RetVT == MVT::i64 && SrcVT == MVT::f64) in selectBitCast()