Lines Matching refs:Offset64
8297 int Offset64, bits<4> opcode> {
8346 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8351 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8356 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8363 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
8364 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
8365 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
8370 int Offset64, bits<4> opcode> {
8418 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8423 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8428 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8435 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
8436 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
8437 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
8441 int Offset128, int Offset64, bits<4> opcode>
8442 : BaseSIMDLdN<Count, asm, veclist, Offset128, Offset64, opcode> {
8454 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8457 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
8461 int Offset128, int Offset64, bits<4> opcode>
8462 : BaseSIMDStN<Count, asm, veclist, Offset128, Offset64, opcode> {
8474 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
8477 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;