Lines Matching refs:Rd
1224 def : InstAlias<asm # "\t$Rd, $imm, $target",
1225 (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
1272 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1273 [(set regtype:$Rd, (node regtype:$Rn))]>,
1275 bits<5> Rd;
1281 let Inst{4-0} = Rd;
1311 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1312 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1315 bits<5> Rd;
1323 let Inst{4-0} = Rd;
1329 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1334 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1365 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1366 asm, "\t$Rd, $Rn, $Rm", "",
1367 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1368 bits<5> Rd;
1376 let Inst{4-0} = Rd;
1433 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
1434 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
1435 bits<5> Rd;
1445 let Inst{4-0} = Rd;
1451 [/*(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))*/]>,
1457 [/*(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))*/]>,
1466 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
1473 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
1474 asm, "\t$Rd, $Rn, $Rm", "",
1475 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
1477 bits<5> Rd;
1485 let Inst{4-0} = Rd;
1504 : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
1505 asm, "\t$Rd, $Rn, $Rm", "",
1506 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
1508 bits<5> Rd;
1519 let Inst{4-0} = Rd;
1563 : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
1564 asm, "\t$Rd, $imm$shift", "", []>,
1566 bits<5> Rd;
1573 let Inst{4-0} = Rd;
1591 : I<(outs regtype:$Rd),
1593 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
1595 bits<5> Rd;
1602 let Inst{4-0} = Rd;
1624 : I<(outs dstRegtype:$Rd), (ins srcRegtype:$Rn, immtype:$imm),
1625 asm, "\t$Rd, $Rn, $imm", "",
1626 [(set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))]>,
1628 bits<5> Rd;
1637 let Inst{4-0} = Rd;
1643 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1644 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1650 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1651 asm, "\t$Rd, $Rn, $Rm", "",
1652 [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
1683 bits<5> Rd;
1695 let Inst{4-0} = Rd;
1704 : I<(outs dstRegtype:$Rd),
1706 asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
1708 bits<5> Rd;
1720 let Inst{4-0} = Rd;
1786 // add Rd, Rb, -imm -> sub Rd, Rn, imm
1787 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1788 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32sp:$Rn,
1790 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1791 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64sp:$Rn,
1861 // Support negative immediates, e.g. adds Rd, Rn, -imm -> subs Rd, Rn, imm
1862 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1863 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32sp:$Rn,
1865 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1866 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64sp:$Rn,
1925 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
1926 asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>,
1928 bits<5> Rd;
1938 let Inst{4-0} = Rd;
1943 [(set GPR32:$Rd,
1951 [(set GPR64:$Rd,
1966 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1967 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1969 bits<5> Rd;
1979 let Inst{4-0} = Rd;
1999 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
2001 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
2003 bits<5> Rd;
2013 let Inst{4-0} = Rd;
2038 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
2039 asm, "\t$Rd, $Rn, $imm", "", pattern>,
2041 bits<5> Rd;
2050 let Inst{4-0} = Rd;
2059 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
2060 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
2091 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
2098 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
2103 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2104 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32:$Rn,
2106 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2107 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64:$Rn,
2115 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
2120 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
2125 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2126 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32:$Rn,
2128 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2129 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64:$Rn,
2134 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
2135 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
2147 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
2152 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
2171 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_shifted_reg32:$Rm))]> {
2175 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
2264 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2265 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2266 [(set regtype:$Rd,
2271 bits<5> Rd;
2282 let Inst{4-0} = Rd;
2296 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2297 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2298 [(set regtype:$Rd,
2304 bits<5> Rd;
2315 let Inst{4-0} = Rd;
3529 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3530 asm, "\t$Rd, $Rn", "", pattern>,
3532 bits<5> Rd;
3542 let Inst{4-0} = Rd;
3549 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3550 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3552 bits<5> Rd;
3563 let Inst{4-0} = Rd;
3570 [(set GPR32:$Rd, (OpN FPR16:$Rn))]> {
3577 [(set GPR64:$Rd, (OpN FPR16:$Rn))]> {
3584 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
3590 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
3596 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3602 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3612 [(set GPR32:$Rd, (OpN (fmul FPR16:$Rn,
3622 [(set GPR64:$Rd, (OpN (fmul FPR16:$Rn,
3631 [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn,
3640 [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn,
3648 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
3657 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
3671 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3672 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3674 bits<5> Rd;
3682 let Inst{4-0} = Rd;
3688 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3689 asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
3691 bits<5> Rd;
3699 let Inst{4-0} = Rd;
3738 [(set FPR16:$Rd,
3748 [(set FPR32:$Rd,
3757 [(set FPR64:$Rd,
3766 [(set FPR16:$Rd,
3775 [(set FPR32:$Rd,
3783 [(set FPR64:$Rd,
3799 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "",
3805 [/*(set (dvt dstType:$Rd), (bitconvert (svt srcType:$Rn)))*/]>,
3807 bits<5> Rd;
3815 let Inst{4-0} = Rd;
3822 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3823 "{\t$Rd"#kind#"$idx, $Rn|"#kind#"\t$Rd$idx, $Rn}", "", []>,
3825 bits<5> Rd;
3833 let Inst{4-0} = Rd;
3842 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3843 "{\t$Rd, $Rn"#kind#"$idx|"#kind#"\t$Rd, $Rn$idx}", "", []>,
3845 bits<5> Rd;
3853 let Inst{4-0} = Rd;
3923 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
3925 bits<5> Rd;
3933 let Inst{4-0} = Rd;
3939 [(set FPR16:$Rd, (fround FPR64:$Rn))]>;
3943 [(set FPR32:$Rd, (fround FPR64:$Rn))]>;
3947 [(set FPR64:$Rd, (fextend FPR16:$Rn))]>;
3951 [(set FPR32:$Rd, (fextend FPR16:$Rn))]>;
3955 [(set FPR64:$Rd, (fextend FPR32:$Rn))]>;
3959 [(set FPR16:$Rd, (fround FPR32:$Rn))]>;
3969 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
3970 [(set (vt regtype:$Rd), (node (vt regtype:$Rn)))]>,
3972 bits<5> Rd;
3979 let Inst{4-0} = Rd;
4005 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
4006 asm, "\t$Rd, $Rn, $Rm", "", pat>,
4008 bits<5> Rd;
4017 let Inst{4-0} = Rd;
4023 [(set (f16 FPR16:$Rd),
4030 [(set (f32 FPR32:$Rd),
4036 [(set (f64 FPR64:$Rd),
4044 [(set FPR16:$Rd, (fneg (node FPR16:$Rn, (f16 FPR16:$Rm))))]> {
4050 [(set FPR32:$Rd, (fneg (node FPR32:$Rn, (f32 FPR32:$Rm))))]> {
4055 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
4067 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
4068 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
4070 bits<5> Rd;
4080 let Inst{4-0} = Rd;
4086 [(set FPR16:$Rd,
4093 [(set FPR32:$Rd,
4099 [(set FPR64:$Rd,
4234 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
4235 asm, "\t$Rd, $Rn, $Rm, $cond", "",
4236 [(set regtype:$Rd,
4240 bits<5> Rd;
4251 let Inst{4-0} = Rd;
4276 : I<(outs regtype:$Rd), (ins fpimmtype:$imm), asm, "\t$Rd, $imm", "",
4277 [(set regtype:$Rd, fpimmtype:$imm)]>,
4279 bits<5> Rd;
4285 let Inst{4-0} = Rd;
4318 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
4319 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4320 "|" # kind # "\t$Rd, $Rn, $Rm|}", "", pattern>,
4322 bits<5> Rd;
4334 let Inst{4-0} = Rd;
4341 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm,
4342 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4343 "|" # kind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4345 bits<5> Rd;
4357 let Inst{4-0} = Rd;
4365 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4368 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4371 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4374 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4377 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4380 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4383 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4391 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
4394 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
4397 [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
4400 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
4403 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
4406 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
4414 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4418 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4422 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4426 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4430 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4434 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4442 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4445 [(set (v16i8 V128:$Rd),
4455 [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
4458 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
4462 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4465 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4468 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4477 [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
4480 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
4484 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4487 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4490 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4499 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
4503 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
4508 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4512 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4516 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4524 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4527 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4530 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4533 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4541 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>;
4544 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
4566 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4570 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
4609 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4610 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4611 "|" # dstkind # "\t$Rd, $Rn}", "", pattern>,
4613 bits<5> Rd;
4626 let Inst{4-0} = Rd;
4634 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm,
4635 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4636 "|" # dstkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4638 bits<5> Rd;
4651 let Inst{4-0} = Rd;
4659 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4662 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4665 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4668 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4671 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4674 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4680 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
4681 "{\t$Rd" # dstkind # ", $Rn" # srckind # ", #" # amount #
4682 "|" # dstkind # "\t$Rd, $Rn, #" # amount # "}", "", []>,
4684 bits<5> Rd;
4692 let Inst{4-0} = Rd;
4717 [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4720 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4723 [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4726 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4729 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4732 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4739 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd),
4743 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
4747 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd),
4751 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
4755 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
4759 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
4768 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
4771 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
4774 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>;
4777 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
4780 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
4783 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
4786 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
4793 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4796 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4799 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4802 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4805 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4808 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4811 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4820 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4823 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4832 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>;
4835 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
4838 [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>;
4841 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
4851 [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>;
4854 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
4858 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4861 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4864 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4872 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4875 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4884 [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>;
4887 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
4891 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4894 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4897 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4905 [(set (v4f16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4908 [(set (v8f16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4912 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4915 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4918 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4926 : I<(outs outreg:$Rd), (ins inreg:$Rn), asm,
4927 "{\t$Rd" # outkind # ", $Rn" # inkind #
4928 "|" # outkind # "\t$Rd, $Rn}", "", pattern>,
4930 bits<5> Rd;
4941 let Inst{4-0} = Rd;
4948 : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm,
4949 "{\t$Rd" # outkind # ", $Rn" # inkind #
4950 "|" # outkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4952 bits<5> Rd;
4963 let Inst{4-0} = Rd;
4970 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4975 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4980 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4984 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
4986 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4987 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
4989 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4990 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
4992 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4999 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
5000 "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
5001 "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
5002 [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
5004 bits<5> Rd;
5017 let Inst{4-0} = Rd;
5099 : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
5100 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
5102 bits<5> Rd;
5113 let Inst{4-0} = Rd;
5120 : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
5121 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
5123 bits<5> Rd;
5134 let Inst{4-0} = Rd;
5163 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
5167 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
5169 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
5182 : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm,
5183 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
5184 "|" # outkind # "\t$Rd, $Rn, $Rm}", "", pattern>,
5186 bits<5> Rd;
5199 let Inst{4-0} = Rd;
5208 : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm,
5209 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
5210 "|" # outkind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
5212 bits<5> Rd;
5225 let Inst{4-0} = Rd;
5237 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5245 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5253 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
5262 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
5265 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
5267 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
5270 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
5272 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
5275 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
5284 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5307 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5311 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5316 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5320 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5329 [(set (v8i16 V128:$Rd),
5334 [(set (v8i16 V128:$Rd),
5340 [(set (v4i32 V128:$Rd),
5345 [(set (v4i32 V128:$Rd),
5351 [(set (v2i64 V128:$Rd),
5356 [(set (v2i64 V128:$Rd),
5368 (add (v8i16 V128:$Rd),
5374 (add (v8i16 V128:$Rd),
5381 (add (v4i32 V128:$Rd),
5387 (add (v4i32 V128:$Rd),
5394 (add (v2i64 V128:$Rd),
5400 (add (v2i64 V128:$Rd),
5410 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5414 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn),
5419 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5423 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5428 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5432 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5443 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5448 (OpNode (v8i16 V128:$Rd),
5455 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5460 (OpNode (v4i32 V128:$Rd),
5467 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5472 (OpNode (v2i64 V128:$Rd),
5483 (Accum (v4i32 V128:$Rd),
5490 (Accum (v4i32 V128:$Rd),
5497 (Accum (v2i64 V128:$Rd),
5504 (Accum (v2i64 V128:$Rd),
5514 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
5518 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
5523 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
5527 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
5532 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
5536 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
5546 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
5547 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" #
5548 "|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "",
5549 [(set (vty regtype:$Rd),
5552 bits<5> Rd;
5564 let Inst{4-0} = Rd;
5581 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5582 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
5583 "|" # kind # "\t$Rd, $Rn, $Rm}", "",
5584 [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>,
5586 bits<5> Rd;
5599 let Inst{4-0} = Rd;
5639 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5640 "\t$Rd, $Rn, $Rm", "", pattern>,
5642 bits<5> Rd;
5653 let Inst{4-0} = Rd;
5660 : I<oops, iops, asm, "\t$Rd, $Rn, $Rm", "$Rd = $dst", pattern>,
5662 bits<5> Rd;
5674 let Inst{4-0} = Rd;
5680 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5686 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5700 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5707 (ins FPR32:$Rd, FPR32:$Rn, FPR32:$Rm),
5710 (ins FPR16:$Rd, FPR16:$Rn, FPR16:$Rm),
5718 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5720 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5723 [(set FPR16:$Rd, (OpNode FPR16:$Rn, FPR16:$Rm))]>;
5735 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5737 [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
5751 "\t$Rd, $Rn, $Rm", cstr, pat>,
5753 bits<5> Rd;
5765 let Inst{4-0} = Rd;
5772 (outs FPR32:$Rd),
5775 (outs FPR64:$Rd),
5777 [(set (i64 FPR64:$Rd), (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5785 (ins FPR32:$Rd, FPR16:$Rn, FPR16:$Rm),
5786 asm, "$Rd = $dst", []>;
5789 (ins FPR64:$Rd, FPR32:$Rn, FPR32:$Rm),
5790 asm, "$Rd = $dst",
5792 (OpNode (i64 FPR64:$Rd), (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5803 : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm,
5804 "\t$Rd, $Rn", "", pat>,
5806 bits<5> Rd;
5818 let Inst{4-0} = Rd;
5825 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm,
5826 "\t$Rd, $Rn", "$Rd = $dst", pat>,
5828 bits<5> Rd;
5838 let Inst{4-0} = Rd;
5845 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
5846 "\t$Rd, $Rn, #" # zero, "", []>,
5848 bits<5> Rd;
5860 let Inst{4-0} = Rd;
5864 : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
5865 [(set (f32 FPR32:$Rd), (int_aarch64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
5867 bits<5> Rd;
5873 let Inst{4-0} = Rd;
5892 def : InstAlias<asm # "\t$Rd, $Rn, #0",
5893 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>;
5894 def : InstAlias<asm # "\t$Rd, $Rn, #0",
5895 (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>;
5897 def : InstAlias<asm # "\t$Rd, $Rn, #0",
5898 (!cast<Instruction>(NAME # v1i16rz) FPR16:$Rd, FPR16:$Rn), 0>;
5908 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
5925 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
5927 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
5930 [(set FPR16:$Rd, (OpNode (f16 FPR16:$Rn)))]>;
5938 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5940 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
5953 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
5955 [(set (i32 FPR32:$dst), (OpNode (i32 FPR32:$Rd), (i32 FPR32:$Rn)))]>;
5960 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))),
5961 (!cast<Instruction>(NAME # v1i64) FPR64:$Rd, FPR64:$Rn)>;
5970 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5983 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5984 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", []>,
5986 bits<5> Rd;
5996 let Inst{4-0} = Rd;
6023 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
6024 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", pattern>,
6026 bits<5> Rd;
6037 let Inst{4-0} = Rd;
6072 [(set FPR16:$Rd, (intOp (v4f16 V64:$Rn)))]>;
6075 [(set FPR16:$Rd, (intOp (v8f16 V128:$Rn)))]>;
6079 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
6092 bits<5> Rd;
6101 let Inst{4-0} = Rd;
6106 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins regtype:$Rn), "dup",
6107 "{\t$Rd" # size # ", $Rn" #
6108 "|" # size # "\t$Rd, $Rn}", "",
6109 [(set (vectype vecreg:$Rd), (AArch64dup regtype:$Rn))]> {
6118 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
6119 "{\t$Rd" # dstkind # ", $Rn" # srckind # "$idx" #
6120 "|" # dstkind # "\t$Rd, $Rn$idx}", "",
6121 [(set (vectype vecreg:$Rd),
6163 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
6164 "{\t$Rd, $Rn" # size # "$idx" #
6165 "|" # size # "\t$Rd, $Rn$idx}", "", pattern> {
6175 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
6243 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
6244 "{\t$Rd" # size # "$idx, $Rn" #
6245 "|" # size # "\t$Rd$idx, $Rn}",
6246 "$Rd = $dst",
6248 (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> {
6255 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
6256 "{\t$Rd" # size # "$idx, $Rn" # size # "$idx2" #
6257 "|" # size # "\t$Rd$idx, $Rn$idx2}",
6258 "$Rd = $dst",
6261 (vectype V128:$Rd),
6568 bits<5> Rd;
6578 let Inst{4-0} = Rd;
6585 : BaseSIMDModifiedImm<Q, op, op2, (outs vectype:$Rd),
6587 "{\t$Rd" # kind # ", $imm8" # opt_shift #
6588 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6598 !con((ins vectype:$Rd, immtype:$imm8), opt_shift_iop),
6599 asm, "{\t$Rd" # kind # ", $imm8" # opt_shift #
6600 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6601 "$Rd = $dst", pattern> {
6674 [(set (v4i16 V64:$dst), (OpNode V64:$Rd,
6679 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
6685 [(set (v2i32 V64:$dst), (OpNode V64:$Rd,
6690 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
6717 : BaseSIMDModifiedImm<Q, op, 0, (outs FPR64:$Rd), (ins simdimmtype10:$imm8), asm,
6718 "\t$Rd, $imm8", "", pattern> {
6733 : I<(outs dst_reg:$Rd), (ins lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx),
6735 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6736 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "", pattern>,
6738 bits<5> Rd;
6754 let Inst{4-0} = Rd;
6764 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm,
6765 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6766 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "$Rd = $dst", pattern>,
6768 bits<5> Rd;
6784 let Inst{4-0} = Rd;
6794 [(set (v4f16 V64:$Rd),
6807 [(set (v8f16 V128:$Rd),
6821 [(set (v2f32 V64:$Rd),
6833 [(set (v4f32 V128:$Rd),
6845 [(set (v2f64 V128:$Rd),
6857 [(set (f16 FPR16Op:$Rd),
6871 [(set (f32 FPR32Op:$Rd),
6883 [(set (f64 FPR64Op:$Rd),
6895 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6899 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6900 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6902 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
6907 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6911 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6912 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6914 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6918 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6922 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6923 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6925 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6929 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6931 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6933 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6935 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6939 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
6941 (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
7026 [(set (v4i16 V64:$Rd),
7039 [(set (v8i16 V128:$Rd),
7052 [(set (v2i32 V64:$Rd),
7064 [(set (v4i32 V128:$Rd),
7084 [(set (i32 FPR32Op:$Rd),
7100 [(set (v4i16 V64:$Rd),
7113 [(set (v8i16 V128:$Rd),
7126 [(set (v2i32 V64:$Rd),
7138 [(set (v4i32 V128:$Rd),
7153 (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
7166 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7179 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7191 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7205 [(set (v4i32 V128:$Rd),
7218 [(set (v4i32 V128:$Rd),
7233 [(set (v2i64 V128:$Rd),
7245 [(set (v2i64 V128:$Rd),
7279 (Accum (v4i32 V128:$Rd),
7292 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
7300 (SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn,
7309 (Accum (v4i32 V128:$Rd),
7326 (Accum (v2i64 V128:$Rd),
7341 (Accum (v2i64 V128:$Rd),
7366 (Accum (i64 FPR64Op:$Rd),
7385 [(set (v4i32 V128:$Rd),
7398 [(set (v4i32 V128:$Rd),
7413 [(set (v2i64 V128:$Rd),
7425 [(set (v2i64 V128:$Rd),
7444 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
7457 (OpNode (v4i32 V128:$Rd),
7472 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
7484 (OpNode (v2i64 V128:$Rd),
7503 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, immtype:$imm),
7504 asm, "\t$Rd, $Rn, $imm", "", pattern>,
7506 bits<5> Rd;
7516 let Inst{4-0} = Rd;
7523 : I<(outs regtype1:$dst), (ins regtype1:$Rd, regtype2:$Rn, immtype:$imm),
7524 asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>,
7526 bits<5> Rd;
7536 let Inst{4-0} = Rd;
7562 [(set (i64 FPR64:$Rd),
7575 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn),
7580 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
7582 (!cast<Instruction>(NAME # "d") FPR64:$Rd, FPR64:$Rn,
7590 [(set (v1i64 FPR64:$Rd),
7619 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn), vecshiftR32:$imm))]> {
7638 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn), (i32 vecshiftL32:$imm)))]> {
7644 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7684 : I<(outs dst_reg:$Rd), (ins src_reg:$Rn, immtype:$imm),
7685 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7686 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "", pattern>,
7688 bits<5> Rd;
7698 let Inst{4-0} = Rd;
7707 : I<(outs vectype1:$dst), (ins vectype1:$Rd, vectype2:$Rn, immtype:$imm),
7708 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7709 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "$Rd = $dst", pattern>,
7711 bits<5> Rd;
7721 let Inst{4-0} = Rd;
7730 [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (i32 imm:$imm)))]> {
7738 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (i32 imm:$imm)))]> {
7746 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> {
7754 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
7762 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
7774 [(set (v4f16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (i32 imm:$imm)))]> {
7782 [(set (v8f16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (i32 imm:$imm)))]> {
7791 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> {
7799 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
7807 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
7818 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
7834 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
7850 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
7868 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
7871 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7873 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
7876 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7878 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
7881 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7890 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7899 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7908 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7917 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7926 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7935 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7944 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7956 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7965 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7974 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7983 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7992 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
8001 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
8010 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
8023 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
8032 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
8041 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
8050 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
8059 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
8068 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8077 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
8090 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
8100 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
8110 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
8120 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
8130 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
8140 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8150 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
8161 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
8169 [(set (v8i16 V128:$Rd),
8177 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
8185 [(set (v4i32 V128:$Rd),
8194 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
8202 [(set (v2i64 V128:$Rd),
9075 (Accum (v4i16 V64:$Rd),
9080 (Accum (v8i16 V128:$Rd),
9085 (Accum (v2i32 V64:$Rd),
9090 (Accum (v4i32 V128:$Rd),
9101 (Accum (v4i16 V64:$Rd),
9116 (Accum (v8i16 V128:$Rd),
9131 (Accum (v2i32 V64:$Rd),
9145 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
9159 FPR32Op:$Rd,
9170 (Accum (v4i32 V128:$Rd),
9182 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
9193 FPR32Op:$Rd,
9214 (Accum (i32 FPR32Op:$Rd),
9234 : I<outs, ins, asm, "{\t$Rd.16b, $Rn.16b|.16b\t$Rd, $Rn}", cstr, pat>,
9236 bits<5> Rd;
9242 let Inst{4-0} = Rd;
9246 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
9247 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
9250 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
9251 "$Rd = $dst",
9253 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
9259 "{\t$Rd" # dst_lhs_kind # ", $Rn" # dst_lhs_kind # ", $Rm.4s" #
9260 "|.4s\t$Rd, $Rn, $Rm}", "$Rd = $dst", pat>,
9262 bits<5> Rd;
9271 let Inst{4-0} = Rd;
9276 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
9278 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
9283 (ins V128:$Rd, V128:$Rn, V128:$Rm),
9285 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
9290 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
9292 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
9299 : I<oops, iops, asm, "{\t$Rd" # kind # ", $Rn" # kind #
9300 "|" # kind # "\t$Rd, $Rn}", cstr, pat>,
9302 bits<5> Rd;
9308 let Inst{4-0} = Rd;
9312 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
9313 (ins V128:$Rd, V128:$Rn),
9315 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
9318 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
9319 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;