Lines Matching refs:AMDGPU
47 if ((AMDGPU::R600_Reg128RegClass.contains(DestReg) || in copyPhysReg()
48 AMDGPU::R600_Reg128VerticalRegClass.contains(DestReg)) && in copyPhysReg()
49 (AMDGPU::R600_Reg128RegClass.contains(SrcReg) || in copyPhysReg()
50 AMDGPU::R600_Reg128VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
52 } else if((AMDGPU::R600_Reg64RegClass.contains(DestReg) || in copyPhysReg()
53 AMDGPU::R600_Reg64VerticalRegClass.contains(DestReg)) && in copyPhysReg()
54 (AMDGPU::R600_Reg64RegClass.contains(SrcReg) || in copyPhysReg()
55 AMDGPU::R600_Reg64VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
62 buildDefaultInstruction(MBB, MI, AMDGPU::MOV, in copyPhysReg()
69 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV, in copyPhysReg()
71 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0)) in copyPhysReg()
92 case AMDGPU::MOV: in isMov()
93 case AMDGPU::MOV_IMM_F32: in isMov()
94 case AMDGPU::MOV_IMM_I32: in isMov()
105 case AMDGPU::RETURN: in isPlaceHolderOpcode()
117 case AMDGPU::CUBE_r600_pseudo: in isCubeOp()
118 case AMDGPU::CUBE_r600_real: in isCubeOp()
119 case AMDGPU::CUBE_eg_pseudo: in isCubeOp()
120 case AMDGPU::CUBE_eg_real: in isCubeOp()
148 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1; in isLDSNoRetInstr()
152 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1; in isLDSRetInstr()
161 case AMDGPU::PRED_X: in canBeConsideredALU()
162 case AMDGPU::INTERP_PAIR_XY: in canBeConsideredALU()
163 case AMDGPU::INTERP_PAIR_ZW: in canBeConsideredALU()
164 case AMDGPU::INTERP_VEC_LOAD: in canBeConsideredALU()
165 case AMDGPU::COPY: in canBeConsideredALU()
166 case AMDGPU::DOT_4: in canBeConsideredALU()
176 return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU); in isTransOnly()
184 return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU); in isVectorOnly()
201 return !AMDGPU::isCompute(MF->getFunction()->getCallingConv()) && in usesVertexCache()
211 return (AMDGPU::isCompute(MF->getFunction()->getCallingConv()) && in usesTextureCache()
218 case AMDGPU::KILLGT: in mustBeLastInClause()
219 case AMDGPU::GROUP_BARRIER: in mustBeLastInClause()
227 return MI.findRegisterUseOperandIdx(AMDGPU::AR_X) != -1; in usesAddressRegister()
231 return MI.findRegisterDefOperandIdx(AMDGPU::AR_X) != -1; in definesAddressRegister()
245 if (AMDGPU::R600_LDS_SRC_REGRegClass.contains(I->getReg())) in readsLDSSrcReg()
253 AMDGPU::OpName::src0, in getSrcIdx()
254 AMDGPU::OpName::src1, in getSrcIdx()
255 AMDGPU::OpName::src2 in getSrcIdx()
264 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel}, in getSelIdx()
265 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel}, in getSelIdx()
266 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel}, in getSelIdx()
267 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X}, in getSelIdx()
268 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y}, in getSelIdx()
269 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z}, in getSelIdx()
270 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W}, in getSelIdx()
271 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X}, in getSelIdx()
272 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y}, in getSelIdx()
273 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z}, in getSelIdx()
274 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W} in getSelIdx()
289 if (MI.getOpcode() == AMDGPU::DOT_4) { in getSrcs()
291 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X}, in getSrcs()
292 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y}, in getSrcs()
293 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z}, in getSrcs()
294 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W}, in getSrcs()
295 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X}, in getSrcs()
296 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y}, in getSrcs()
297 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z}, in getSrcs()
298 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}, in getSrcs()
305 if (Reg == AMDGPU::ALU_CONST) { in getSrcs()
317 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel}, in getSrcs()
318 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel}, in getSrcs()
319 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel}, in getSrcs()
328 if (Reg == AMDGPU::ALU_CONST) { in getSrcs()
334 if (Reg == AMDGPU::ALU_LITERAL_X) { in getSrcs()
336 MI.getOperand(getOperandIdx(MI.getOpcode(), AMDGPU::OpName::literal)); in getSrcs()
360 if (Reg == AMDGPU::OQAP) { in ExtractSrcs()
452 if (Src.first == GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) { in isLegalUpTo()
558 AMDGPU::OpName::bank_swizzle); in fitsReadPortLimitations()
630 if (Src.first->getReg() == AMDGPU::ALU_LITERAL_X) in fitsConstReadLimitations()
634 if (Src.first->getReg() == AMDGPU::ALU_CONST) in fitsConstReadLimitations()
636 if (AMDGPU::R600_KC0RegClass.contains(Src.first->getReg()) || in fitsConstReadLimitations()
637 AMDGPU::R600_KC1RegClass.contains(Src.first->getReg())) { in fitsConstReadLimitations()
656 case AMDGPU::PRED_X: in isPredicateSetter()
678 return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND; in isJump()
682 return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 || in isBranch()
683 Opcode == AMDGPU::BRANCH_COND_f32; in isBranch()
707 while (I != MBB.begin() && std::prev(I)->getOpcode() == AMDGPU::JUMP) { in analyzeBranch()
719 if (LastOpc == AMDGPU::JUMP) { in analyzeBranch()
722 } else if (LastOpc == AMDGPU::JUMP_COND) { in analyzeBranch()
730 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); in analyzeBranch()
741 if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) { in analyzeBranch()
750 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false)); in analyzeBranch()
762 if (It->getOpcode() == AMDGPU::CF_ALU || in FindLastAluClause()
763 It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE) in FindLastAluClause()
778 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB); in InsertBranch()
786 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND)) in InsertBranch()
788 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); in InsertBranch()
792 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU); in InsertBranch()
793 CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE)); in InsertBranch()
801 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND)) in InsertBranch()
803 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); in InsertBranch()
804 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB); in InsertBranch()
808 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU); in InsertBranch()
809 CfAlu->setDesc(get(AMDGPU::CF_ALU_PUSH_BEFORE)); in InsertBranch()
829 case AMDGPU::JUMP_COND: { in RemoveBranch()
836 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE); in RemoveBranch()
837 CfAlu->setDesc(get(AMDGPU::CF_ALU)); in RemoveBranch()
840 case AMDGPU::JUMP: in RemoveBranch()
854 case AMDGPU::JUMP_COND: { in RemoveBranch()
861 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE); in RemoveBranch()
862 CfAlu->setDesc(get(AMDGPU::CF_ALU)); in RemoveBranch()
865 case AMDGPU::JUMP: in RemoveBranch()
880 case AMDGPU::PRED_SEL_ONE: in isPredicated()
881 case AMDGPU::PRED_SEL_ZERO: in isPredicated()
882 case AMDGPU::PREDICATE_BIT: in isPredicated()
893 if (MI.getOpcode() == AMDGPU::KILLGT) { in isPredicable()
895 } else if (MI.getOpcode() == AMDGPU::CF_ALU) { in isPredicable()
966 case AMDGPU::PRED_SEL_ZERO: in ReverseBranchCondition()
967 MO2.setReg(AMDGPU::PRED_SEL_ONE); in ReverseBranchCondition()
969 case AMDGPU::PRED_SEL_ONE: in ReverseBranchCondition()
970 MO2.setReg(AMDGPU::PRED_SEL_ZERO); in ReverseBranchCondition()
994 if (MI.getOpcode() == AMDGPU::CF_ALU) { in PredicateInstruction()
999 if (MI.getOpcode() == AMDGPU::DOT_4) { in PredicateInstruction()
1000 MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_X)) in PredicateInstruction()
1002 MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Y)) in PredicateInstruction()
1004 MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Z)) in PredicateInstruction()
1006 MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_W)) in PredicateInstruction()
1009 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
1017 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
1047 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::addr); in expandPostRAPseudo()
1052 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::chan); in expandPostRAPseudo()
1055 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); in expandPostRAPseudo()
1060 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1069 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::val); in expandPostRAPseudo()
1074 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1089 case AMDGPU::R600_EXTRACT_ELT_V2: in expandPostRAPseudo()
1090 case AMDGPU::R600_EXTRACT_ELT_V4: in expandPostRAPseudo()
1096 case AMDGPU::R600_INSERT_ELT_V2: in expandPostRAPseudo()
1097 case AMDGPU::R600_INSERT_ELT_V4: in expandPostRAPseudo()
1120 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index); in reserveIndirectRegisters()
1123 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan); in reserveIndirectRegisters()
1130 return &AMDGPU::R600_TReg32_XRegClass; in getIndirectAddrRegClass()
1148 case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break; in buildIndirectWrite()
1149 case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectWrite()
1150 case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectWrite()
1151 case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break; in buildIndirectWrite()
1153 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg, in buildIndirectWrite()
1154 AMDGPU::AR_X, OffsetReg); in buildIndirectWrite()
1155 setImmOperand(*MOVA, AMDGPU::OpName::write, 0); in buildIndirectWrite()
1157 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV, in buildIndirectWrite()
1159 .addReg(AMDGPU::AR_X, in buildIndirectWrite()
1161 setImmOperand(*Mov, AMDGPU::OpName::dst_rel, 1); in buildIndirectWrite()
1180 case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break; in buildIndirectRead()
1181 case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectRead()
1182 case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectRead()
1183 case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break; in buildIndirectRead()
1185 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg, in buildIndirectRead()
1186 AMDGPU::AR_X, in buildIndirectRead()
1188 setImmOperand(*MOVA, AMDGPU::OpName::write, 0); in buildIndirectRead()
1189 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV, in buildIndirectRead()
1192 .addReg(AMDGPU::AR_X, in buildIndirectRead()
1194 setImmOperand(*Mov, AMDGPU::OpName::src0_rel, 1); in buildIndirectRead()
1294 .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel in buildDefaultInstruction()
1315 OPERAND_CASE(AMDGPU::OpName::update_exec_mask) in getSlotedOps()
1316 OPERAND_CASE(AMDGPU::OpName::update_pred) in getSlotedOps()
1317 OPERAND_CASE(AMDGPU::OpName::write) in getSlotedOps()
1318 OPERAND_CASE(AMDGPU::OpName::omod) in getSlotedOps()
1319 OPERAND_CASE(AMDGPU::OpName::dst_rel) in getSlotedOps()
1320 OPERAND_CASE(AMDGPU::OpName::clamp) in getSlotedOps()
1321 OPERAND_CASE(AMDGPU::OpName::src0) in getSlotedOps()
1322 OPERAND_CASE(AMDGPU::OpName::src0_neg) in getSlotedOps()
1323 OPERAND_CASE(AMDGPU::OpName::src0_rel) in getSlotedOps()
1324 OPERAND_CASE(AMDGPU::OpName::src0_abs) in getSlotedOps()
1325 OPERAND_CASE(AMDGPU::OpName::src0_sel) in getSlotedOps()
1326 OPERAND_CASE(AMDGPU::OpName::src1) in getSlotedOps()
1327 OPERAND_CASE(AMDGPU::OpName::src1_neg) in getSlotedOps()
1328 OPERAND_CASE(AMDGPU::OpName::src1_rel) in getSlotedOps()
1329 OPERAND_CASE(AMDGPU::OpName::src1_abs) in getSlotedOps()
1330 OPERAND_CASE(AMDGPU::OpName::src1_sel) in getSlotedOps()
1331 OPERAND_CASE(AMDGPU::OpName::pred_sel) in getSlotedOps()
1342 assert (MI->getOpcode() == AMDGPU::DOT_4 && "Not Implemented"); in buildSlotOfVectorInstruction()
1345 Opcode = AMDGPU::DOT4_r600; in buildSlotOfVectorInstruction()
1347 Opcode = AMDGPU::DOT4_eg; in buildSlotOfVectorInstruction()
1350 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot))); in buildSlotOfVectorInstruction()
1352 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot))); in buildSlotOfVectorInstruction()
1356 AMDGPU::OpName::update_exec_mask, in buildSlotOfVectorInstruction()
1357 AMDGPU::OpName::update_pred, in buildSlotOfVectorInstruction()
1358 AMDGPU::OpName::write, in buildSlotOfVectorInstruction()
1359 AMDGPU::OpName::omod, in buildSlotOfVectorInstruction()
1360 AMDGPU::OpName::dst_rel, in buildSlotOfVectorInstruction()
1361 AMDGPU::OpName::clamp, in buildSlotOfVectorInstruction()
1362 AMDGPU::OpName::src0_neg, in buildSlotOfVectorInstruction()
1363 AMDGPU::OpName::src0_rel, in buildSlotOfVectorInstruction()
1364 AMDGPU::OpName::src0_abs, in buildSlotOfVectorInstruction()
1365 AMDGPU::OpName::src0_sel, in buildSlotOfVectorInstruction()
1366 AMDGPU::OpName::src1_neg, in buildSlotOfVectorInstruction()
1367 AMDGPU::OpName::src1_rel, in buildSlotOfVectorInstruction()
1368 AMDGPU::OpName::src1_abs, in buildSlotOfVectorInstruction()
1369 AMDGPU::OpName::src1_sel, in buildSlotOfVectorInstruction()
1373 getSlotedOps(AMDGPU::OpName::pred_sel, Slot))); in buildSlotOfVectorInstruction()
1374 MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel)) in buildSlotOfVectorInstruction()
1391 MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg, in buildMovImm()
1392 AMDGPU::ALU_LITERAL_X); in buildMovImm()
1393 setImmOperand(*MovImm, AMDGPU::OpName::literal, Imm); in buildMovImm()
1400 return buildDefaultInstruction(*MBB, I, AMDGPU::MOV, DstReg, SrcReg); in buildMovInstr()
1408 return AMDGPU::getNamedOperandIdx(Opcode, Op); in getOperandIdx()
1439 FlagIndex = getOperandIdx(MI, AMDGPU::OpName::clamp); in getFlagOp()
1442 FlagIndex = getOperandIdx(MI, AMDGPU::OpName::write); in getFlagOp()
1446 FlagIndex = getOperandIdx(MI, AMDGPU::OpName::last); in getFlagOp()
1451 FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src0_neg); in getFlagOp()
1454 FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src1_neg); in getFlagOp()
1457 FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src2_neg); in getFlagOp()
1468 FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src0_abs); in getFlagOp()
1471 FlagIndex = getOperandIdx(MI, AMDGPU::OpName::src1_abs); in getFlagOp()