57   void swapOperands(MachineInstr &Inst) const;
59   void lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
60                       MachineInstr &Inst) const;
62   void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
63                                MachineInstr &Inst, unsigned Opcode) const;
65   void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
66                                 MachineInstr &Inst, unsigned Opcode) const;
68   void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
69                             MachineInstr &Inst) const;
70   void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
71                            MachineInstr &Inst) const;
75     SmallVectorImpl<MachineInstr *> &Worklist) const;
78   addSCCDefUsersToVALUWorklist(MachineInstr &SCCDefInst,
79                                SmallVectorImpl<MachineInstr *> &Worklist) const;
82   getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
84   bool checkInstOffsetsDoNotOverlap(MachineInstr &MIa, MachineInstr &MIb) const;
86   unsigned findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
89   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
106   bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
113   bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
117   bool shouldClusterMemOps(MachineInstr &FirstLdSt, MachineInstr &SecondLdSt,
124   unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI,
139   bool expandPostRAPseudo(MachineInstr &MI) const override;
147   int commuteOpcode(const MachineInstr &MI) const;
149   bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
167   areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
170   bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
175   MachineInstr *convertToThreeAddress(MachineFunction::iterator &MBB,
176                                       MachineInstr &MI,
179   bool isSchedulingBoundary(const MachineInstr &MI,
183   static bool isSALU(const MachineInstr &MI) {  in isSALU()
191   static bool isVALU(const MachineInstr &MI) {  in isVALU()
199   static bool isVMEM(const MachineInstr &MI) {  in isVMEM()
207   static bool isSOP1(const MachineInstr &MI) {  in isSOP1()
215   static bool isSOP2(const MachineInstr &MI) {  in isSOP2()
223   static bool isSOPC(const MachineInstr &MI) {  in isSOPC()
231   static bool isSOPK(const MachineInstr &MI) {  in isSOPK()
239   static bool isSOPP(const MachineInstr &MI) {  in isSOPP()
247   static bool isVOP1(const MachineInstr &MI) {  in isVOP1()
255   static bool isVOP2(const MachineInstr &MI) {  in isVOP2()
263   static bool isVOP3(const MachineInstr &MI) {  in isVOP3()
271   static bool isVOPC(const MachineInstr &MI) {  in isVOPC()
279   static bool isMUBUF(const MachineInstr &MI) {  in isMUBUF()
287   static bool isMTBUF(const MachineInstr &MI) {  in isMTBUF()
295   static bool isSMRD(const MachineInstr &MI) {  in isSMRD()
303   static bool isDS(const MachineInstr &MI) {  in isDS()
311   static bool isMIMG(const MachineInstr &MI) {  in isMIMG()
319   static bool isGather4(const MachineInstr &MI) {  in isGather4()
327   static bool isFLAT(const MachineInstr &MI) {  in isFLAT()
335   static bool isWQM(const MachineInstr &MI) {  in isWQM()
343   static bool isVGPRSpill(const MachineInstr &MI) {  in isVGPRSpill()
351   static bool isDPP(const MachineInstr &MI) {  in isDPP()
359   static bool isScalarUnit(const MachineInstr &MI) {  in isScalarUnit()
363   static bool usesVM_CNT(const MachineInstr &MI) {  in usesVM_CNT()
367   bool isVGPRCopy(const MachineInstr &MI) const {  in isVGPRCopy()
379   bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
395   bool hasModifiersSet(const MachineInstr &MI,
398   bool verifyInstruction(const MachineInstr &MI,
401   static unsigned getVALUOp(const MachineInstr &MI);
403   bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
410   const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
429   unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {  in getOpSize()
435   bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
446   void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
450   bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
468   void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
471   void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;
477   unsigned readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,
480   void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
484   void legalizeOperands(MachineInstr &MI) const;
489   void moveToVALU(MachineInstr &MI) const;
499   unsigned getNumWaitStates(const MachineInstr &MI) const;
504   MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
507   const MachineOperand *getNamedOperand(const MachineInstr &MI,  in getNamedOperand()
509     return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);  in getNamedOperand()
513   int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {  in getNamedImmOperand()
521   bool isLowLatencyInstruction(const MachineInstr &MI) const;
522   bool isHighLatencyInstruction(const MachineInstr &MI) const;
530   unsigned getInstSizeInBytes(const MachineInstr &MI) const;