Lines Matching refs:sdst
756 op, opName, (outs SReg_32:$sdst), (ins SSrc_32:$src0),
757 opName#" $sdst, $src0", pattern
761 op, opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0),
762 opName#" $sdst, $src0", pattern
767 def "" : SOP1_Pseudo <opName, (outs SReg_64:$sdst), (ins), pattern>;
769 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$sdst), (ins),
770 opName#" $sdst"> {
774 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$sdst), (ins),
775 opName#" $sdst"> {
786 let sdst = 0;
791 let sdst = 0;
797 op, opName, (outs SReg_32:$sdst), (ins SSrc_64:$src0),
798 opName#" $sdst, $src0", pattern
803 op, opName, (outs SReg_64:$sdst), (ins SSrc_32:$src0),
804 opName#" $sdst, $src0", pattern
816 // let sdst = xxx in {
818 field bits<7> sdst = 0;
851 op, opName, (outs SReg_32:$sdst), (ins SSrc_32:$src0, SSrc_32:$src1),
852 opName#" $sdst, $src0, $src1", pattern
856 op, opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0, SSrc_64:$src1),
857 opName#" $sdst, $src0, $src1", pattern
861 op, opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0, SSrc_32:$src1),
862 opName#" $sdst, $src0, $src1", pattern
866 op, opName, (outs SReg_64:$sdst), (ins SSrc_32:$src0, SSrc_32:$src1),
867 opName#" $sdst, $src0, $src1", pattern
929 def "" : SOPK_Pseudo <opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
932 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
933 opName#" $sdst, $simm16">;
935 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
936 opName#" $sdst, $simm16">;
947 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
952 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
958 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
959 " $sdst, $simm16"
1073 let sbase = 0, soff = 0, sdst = sdst_ in {
1095 let sdst = 0;
1101 SMRD_SOFF_Real_vi<op, opName, (outs SReg_64:$sdst), (ins),
1102 opName#" $sdst", [(set i64:$sdst, (node))]> {
1114 op, opName#"_IMM", (outs dstClass:$sdst),
1116 opName#" $sdst, $sbase, $offset", []
1120 (outs dstClass:$sdst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
1121 opName#" $sdst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
1127 op, opName#"_SGPR", (outs dstClass:$sdst),
1129 opName#" $sdst, $sbase, $soff", []
1329 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1342 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1357 "$sdst",
1359 ""); // use $sdst for VOPC
1506 let Asm64 = "$vdst, $sdst, $src0, $src1";
1508 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
1521 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2";
1523 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
1544 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
1545 let Asm64 = "$vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod";
1565 let Outs64 = (outs DstRC:$sdst);
1570 let Asm64 = "$sdst, $src0_modifiers, $src1";
1624 // This class is used only with VOPC instructions. Use $sdst for out operand
1635 (inst p.DstRC:$sdst),
1638 (inst p.DstRC:$sdst, p.Src0RC32:$src0),
1641 (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
2035 // Same as VOP3b_2_3_m but no 2nd destination (sdst), e.g. v_cndmask_b32.
2342 defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$sdst), p.Ins64, opName#p.Asm64, pat64,
2355 defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$sdst), p.Ins64, opName#p.Asm64, pat64,
2373 [(set i1:$sdst,
2378 [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
2387 [(set i1:$sdst,
2389 [(set i1:$sdst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),