318     bool fixupImmediateBr(ImmBranch &Br);
319     bool fixupConditionalBr(ImmBranch &Br);
320     bool fixupUnconditionalBr(ImmBranch &Br);
1675 bool ARMConstantIslands::fixupImmediateBr(ImmBranch &Br) {  in fixupImmediateBr()  argument
1676   MachineInstr *MI = Br.MI;  in fixupImmediateBr()
1680   if (isBBInRange(MI, DestBB, Br.MaxDisp))  in fixupImmediateBr()
1683   if (!Br.isCond)  in fixupImmediateBr()
1684     return fixupUnconditionalBr(Br);  in fixupImmediateBr()
1685   return fixupConditionalBr(Br);  in fixupImmediateBr()
1693 ARMConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {  in fixupUnconditionalBr()  argument
1694   MachineInstr *MI = Br.MI;  in fixupUnconditionalBr()
1700   Br.MaxDisp = (1 << 21) * 2;  in fixupUnconditionalBr()
1716 ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {  in fixupConditionalBr()  argument
1717   MachineInstr *MI = Br.MI;  in fixupConditionalBr()
1741         BMI->getOpcode() == Br.UncondBr) {  in fixupConditionalBr()
1750       if (isBBInRange(MI, NewDest, Br.MaxDisp)) {  in fixupConditionalBr()
1780   Br.MI = &MBB->back();  in fixupConditionalBr()
1783     BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB)  in fixupConditionalBr()
1786     BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);  in fixupConditionalBr()
1788   unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);  in fixupConditionalBr()
1789   ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));  in fixupConditionalBr()
1901     ImmBranch &Br = ImmBranches[i-1];  in optimizeThumb2Branches()  local
1902     unsigned Opcode = Br.MI->getOpcode();  in optimizeThumb2Branches()
1922       MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();  in optimizeThumb2Branches()
1923       if (isBBInRange(Br.MI, DestBB, MaxOffs)) {  in optimizeThumb2Branches()
1924         DEBUG(dbgs() << "Shrink branch: " << *Br.MI);  in optimizeThumb2Branches()
1925         Br.MI->setDesc(TII->get(NewOpc));  in optimizeThumb2Branches()
1926         MachineBasicBlock *MBB = Br.MI->getParent();  in optimizeThumb2Branches()
1934     Opcode = Br.MI->getOpcode();  in optimizeThumb2Branches()
1940     if (!Br.MI->killsRegister(ARM::CPSR))  in optimizeThumb2Branches()
1945     ARMCC::CondCodes Pred = getInstrPredicate(*Br.MI, PredReg);  in optimizeThumb2Branches()
1952     MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();  in optimizeThumb2Branches()
1955     unsigned BrOffset = getOffsetOf(Br.MI) + 4 - 2;  in optimizeThumb2Branches()
1958       MachineBasicBlock::iterator CmpMI = Br.MI;  in optimizeThumb2Branches()
1959       if (CmpMI != Br.MI->getParent()->begin()) {  in optimizeThumb2Branches()
1967             MachineBasicBlock *MBB = Br.MI->getParent();  in optimizeThumb2Branches()
1968             DEBUG(dbgs() << "Fold: " << *CmpMI << " and: " << *Br.MI);  in optimizeThumb2Branches()
1970               BuildMI(*MBB, CmpMI, Br.MI->getDebugLoc(), TII->get(NewOpc))  in optimizeThumb2Branches()
1971               .addReg(Reg).addMBB(DestBB,Br.MI->getOperand(0).getTargetFlags());  in optimizeThumb2Branches()
1973             Br.MI->eraseFromParent();  in optimizeThumb2Branches()
1974             Br.MI = NewBR;  in optimizeThumb2Branches()