Lines Matching refs:ARM
150 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
151 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
152 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
153 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
154 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
155 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
157 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
158 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,fals…
159 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
160 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,fals…
162 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
163 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
164 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
165 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
166 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
167 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
168 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
169 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
170 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
171 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
173 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
174 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
175 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,fa…
176 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
177 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
178 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,fa…
179 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
180 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
181 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,fal…
183 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
184 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
185 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
186 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
187 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
188 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
190 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
191 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
192 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
193 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
194 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
195 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
196 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
197 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
198 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
199 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
201 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
202 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
203 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
204 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
205 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
206 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
208 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
209 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
210 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
211 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
212 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
213 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
214 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
215 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
216 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
218 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
219 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
220 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
221 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
222 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
223 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
225 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
226 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
227 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
228 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
229 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
230 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
231 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
232 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
233 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
234 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
236 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
237 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
238 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
239 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
240 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
241 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
243 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
244 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
245 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
246 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
247 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
248 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
249 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
250 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
251 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
253 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
254 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
255 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
256 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
257 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
258 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
260 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
261 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false…
262 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,f…
263 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
264 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false…
265 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,…
267 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
268 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
269 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
270 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
271 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
272 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
273 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
274 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
275 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
276 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
278 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
279 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
280 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,f…
281 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
282 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
283 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,f…
284 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
285 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
286 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,fa…
288 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
289 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
290 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
291 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
292 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
293 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
294 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
295 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
296 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
297 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
299 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
300 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
301 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
302 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
303 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
304 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
306 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
307 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
308 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
309 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
310 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
311 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
312 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
313 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
314 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
316 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
317 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
318 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
319 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
320 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
321 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
322 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
323 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
324 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
325 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
327 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
328 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
329 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
330 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
331 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
332 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
334 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
335 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
336 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
337 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
338 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
339 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
340 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
341 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
342 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
372 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
373 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
374 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
375 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
377 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
378 D1 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
379 D2 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
380 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
383 D0 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
384 D1 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
385 D2 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
386 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
672 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; in ExpandMOV32BitImm()
678 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { in ExpandMOV32BitImm()
683 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); in ExpandMOV32BitImm()
684 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) in ExpandMOV32BitImm()
705 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { in ExpandMOV32BitImm()
706 LO16Opc = ARM::t2MOVi16; in ExpandMOV32BitImm()
707 HI16Opc = ARM::t2MOVTi16; in ExpandMOV32BitImm()
709 LO16Opc = ARM::MOVi16; in ExpandMOV32BitImm()
710 HI16Opc = ARM::MOVTi16; in ExpandMOV32BitImm()
812 if (LdrexOp == ARM::t2LDREX) in ExpandCMP_SWAP()
816 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; in ExpandCMP_SWAP()
820 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; in ExpandCMP_SWAP()
824 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
840 if (StrexOp == ARM::t2STREX) in ExpandCMP_SWAP()
844 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; in ExpandCMP_SWAP()
851 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
873 unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair()
874 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair()
894 unsigned DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); in ExpandCMP_SWAP_64()
895 unsigned DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1); in ExpandCMP_SWAP_64()
896 unsigned DesiredLo = TRI->getSubReg(Desired.getReg(), ARM::gsub_0); in ExpandCMP_SWAP_64()
897 unsigned DesiredHi = TRI->getSubReg(Desired.getReg(), ARM::gsub_1); in ExpandCMP_SWAP_64()
923 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD; in ExpandCMP_SWAP_64()
930 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; in ExpandCMP_SWAP_64()
935 unsigned SBCrr = IsThumb ? ARM::t2SBCrr : ARM::SBCrr; in ExpandCMP_SWAP_64()
941 MIB.addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
943 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; in ExpandCMP_SWAP_64()
947 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
959 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD; in ExpandCMP_SWAP_64()
965 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; in ExpandCMP_SWAP_64()
972 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
997 case ARM::TCRETURNdi: in ExpandMI()
998 case ARM::TCRETURNri: { in ExpandMI()
1012 if (RetOpcode == ARM::TCRETURNdi) { in ExpandMI()
1015 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) in ExpandMI()
1016 : ARM::TAILJMPd; in ExpandMI()
1030 } else if (RetOpcode == ARM::TCRETURNri) { in ExpandMI()
1032 TII.get(STI->isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)) in ExpandMI()
1045 case ARM::VMOVScc: in ExpandMI()
1046 case ARM::VMOVDcc: { in ExpandMI()
1047 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD; in ExpandMI()
1057 case ARM::t2MOVCCr: in ExpandMI()
1058 case ARM::MOVCCr: { in ExpandMI()
1059 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; in ExpandMI()
1070 case ARM::MOVCCsi: { in ExpandMI()
1071 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
1082 case ARM::MOVCCsr: { in ExpandMI()
1083 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), in ExpandMI()
1095 case ARM::t2MOVCCi16: in ExpandMI()
1096 case ARM::MOVCCi16: { in ExpandMI()
1097 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; in ExpandMI()
1106 case ARM::t2MOVCCi: in ExpandMI()
1107 case ARM::MOVCCi: { in ExpandMI()
1108 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; in ExpandMI()
1119 case ARM::t2MVNCCi: in ExpandMI()
1120 case ARM::MVNCCi: { in ExpandMI()
1121 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; in ExpandMI()
1132 case ARM::t2MOVCClsl: in ExpandMI()
1133 case ARM::t2MOVCClsr: in ExpandMI()
1134 case ARM::t2MOVCCasr: in ExpandMI()
1135 case ARM::t2MOVCCror: { in ExpandMI()
1138 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; in ExpandMI()
1139 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; in ExpandMI()
1140 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; in ExpandMI()
1141 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; in ExpandMI()
1154 case ARM::Int_eh_sjlj_dispatchsetup: { in ExpandMI()
1169 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
1172 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
1175 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
1189 ARM::t2BICri : ARM::BICri; in ExpandMI()
1191 TII->get(bicOpc), ARM::R6) in ExpandMI()
1192 .addReg(ARM::R6, RegState::Kill) in ExpandMI()
1201 case ARM::MOVsrl_flag: in ExpandMI()
1202 case ARM::MOVsra_flag: { in ExpandMI()
1204 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
1207 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? in ExpandMI()
1210 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
1214 case ARM::RRX: { in ExpandMI()
1217 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi), in ExpandMI()
1226 case ARM::tTPsoft: in ExpandMI()
1227 case ARM::TPsoft: { in ExpandMI()
1229 if (Opcode == ARM::tTPsoft) in ExpandMI()
1231 TII->get( ARM::tBL)) in ExpandMI()
1236 TII->get( ARM::BL)) in ExpandMI()
1244 case ARM::tLDRpci_pic: in ExpandMI()
1245 case ARM::t2LDRpci_pic: { in ExpandMI()
1246 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) in ExpandMI()
1247 ? ARM::tLDRpci : ARM::t2LDRpci; in ExpandMI()
1256 TII->get(ARM::tPICADD)) in ExpandMI()
1265 case ARM::LDRLIT_ga_abs: in ExpandMI()
1266 case ARM::LDRLIT_ga_pcrel: in ExpandMI()
1267 case ARM::LDRLIT_ga_pcrel_ldr: in ExpandMI()
1268 case ARM::tLDRLIT_ga_abs: in ExpandMI()
1269 case ARM::tLDRLIT_ga_pcrel: { in ExpandMI()
1275 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs; in ExpandMI()
1277 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs; in ExpandMI()
1278 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci; in ExpandMI()
1281 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) in ExpandMI()
1282 : ARM::tPICADD; in ExpandMI()
1318 case ARM::MOV_ga_pcrel: in ExpandMI()
1319 case ARM::MOV_ga_pcrel_ldr: in ExpandMI()
1320 case ARM::t2MOV_ga_pcrel: { in ExpandMI()
1328 bool isARM = Opcode != ARM::t2MOV_ga_pcrel; in ExpandMI()
1329 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; in ExpandMI()
1330 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; in ExpandMI()
1334 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) in ExpandMI()
1335 : ARM::tPICADD; in ExpandMI()
1352 if (Opcode == ARM::MOV_ga_pcrel_ldr) in ExpandMI()
1360 case ARM::MOVi32imm: in ExpandMI()
1361 case ARM::MOVCCi32imm: in ExpandMI()
1362 case ARM::t2MOVi32imm: in ExpandMI()
1363 case ARM::t2MOVCCi32imm: in ExpandMI()
1367 case ARM::SUBS_PC_LR: { in ExpandMI()
1369 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) in ExpandMI()
1370 .addReg(ARM::LR) in ExpandMI()
1374 .addReg(ARM::CPSR, RegState::Undef); in ExpandMI()
1379 case ARM::VLDMQIA: { in ExpandMI()
1380 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI()
1397 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0); in ExpandMI()
1398 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); in ExpandMI()
1410 case ARM::VSTMQIA: { in ExpandMI()
1411 unsigned NewOpc = ARM::VSTMDIA; in ExpandMI()
1428 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); in ExpandMI()
1429 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); in ExpandMI()
1442 case ARM::VLD2q8Pseudo: in ExpandMI()
1443 case ARM::VLD2q16Pseudo: in ExpandMI()
1444 case ARM::VLD2q32Pseudo: in ExpandMI()
1445 case ARM::VLD2q8PseudoWB_fixed: in ExpandMI()
1446 case ARM::VLD2q16PseudoWB_fixed: in ExpandMI()
1447 case ARM::VLD2q32PseudoWB_fixed: in ExpandMI()
1448 case ARM::VLD2q8PseudoWB_register: in ExpandMI()
1449 case ARM::VLD2q16PseudoWB_register: in ExpandMI()
1450 case ARM::VLD2q32PseudoWB_register: in ExpandMI()
1451 case ARM::VLD3d8Pseudo: in ExpandMI()
1452 case ARM::VLD3d16Pseudo: in ExpandMI()
1453 case ARM::VLD3d32Pseudo: in ExpandMI()
1454 case ARM::VLD1d64TPseudo: in ExpandMI()
1455 case ARM::VLD1d64TPseudoWB_fixed: in ExpandMI()
1456 case ARM::VLD3d8Pseudo_UPD: in ExpandMI()
1457 case ARM::VLD3d16Pseudo_UPD: in ExpandMI()
1458 case ARM::VLD3d32Pseudo_UPD: in ExpandMI()
1459 case ARM::VLD3q8Pseudo_UPD: in ExpandMI()
1460 case ARM::VLD3q16Pseudo_UPD: in ExpandMI()
1461 case ARM::VLD3q32Pseudo_UPD: in ExpandMI()
1462 case ARM::VLD3q8oddPseudo: in ExpandMI()
1463 case ARM::VLD3q16oddPseudo: in ExpandMI()
1464 case ARM::VLD3q32oddPseudo: in ExpandMI()
1465 case ARM::VLD3q8oddPseudo_UPD: in ExpandMI()
1466 case ARM::VLD3q16oddPseudo_UPD: in ExpandMI()
1467 case ARM::VLD3q32oddPseudo_UPD: in ExpandMI()
1468 case ARM::VLD4d8Pseudo: in ExpandMI()
1469 case ARM::VLD4d16Pseudo: in ExpandMI()
1470 case ARM::VLD4d32Pseudo: in ExpandMI()
1471 case ARM::VLD1d64QPseudo: in ExpandMI()
1472 case ARM::VLD1d64QPseudoWB_fixed: in ExpandMI()
1473 case ARM::VLD4d8Pseudo_UPD: in ExpandMI()
1474 case ARM::VLD4d16Pseudo_UPD: in ExpandMI()
1475 case ARM::VLD4d32Pseudo_UPD: in ExpandMI()
1476 case ARM::VLD4q8Pseudo_UPD: in ExpandMI()
1477 case ARM::VLD4q16Pseudo_UPD: in ExpandMI()
1478 case ARM::VLD4q32Pseudo_UPD: in ExpandMI()
1479 case ARM::VLD4q8oddPseudo: in ExpandMI()
1480 case ARM::VLD4q16oddPseudo: in ExpandMI()
1481 case ARM::VLD4q32oddPseudo: in ExpandMI()
1482 case ARM::VLD4q8oddPseudo_UPD: in ExpandMI()
1483 case ARM::VLD4q16oddPseudo_UPD: in ExpandMI()
1484 case ARM::VLD4q32oddPseudo_UPD: in ExpandMI()
1485 case ARM::VLD3DUPd8Pseudo: in ExpandMI()
1486 case ARM::VLD3DUPd16Pseudo: in ExpandMI()
1487 case ARM::VLD3DUPd32Pseudo: in ExpandMI()
1488 case ARM::VLD3DUPd8Pseudo_UPD: in ExpandMI()
1489 case ARM::VLD3DUPd16Pseudo_UPD: in ExpandMI()
1490 case ARM::VLD3DUPd32Pseudo_UPD: in ExpandMI()
1491 case ARM::VLD4DUPd8Pseudo: in ExpandMI()
1492 case ARM::VLD4DUPd16Pseudo: in ExpandMI()
1493 case ARM::VLD4DUPd32Pseudo: in ExpandMI()
1494 case ARM::VLD4DUPd8Pseudo_UPD: in ExpandMI()
1495 case ARM::VLD4DUPd16Pseudo_UPD: in ExpandMI()
1496 case ARM::VLD4DUPd32Pseudo_UPD: in ExpandMI()
1500 case ARM::VST2q8Pseudo: in ExpandMI()
1501 case ARM::VST2q16Pseudo: in ExpandMI()
1502 case ARM::VST2q32Pseudo: in ExpandMI()
1503 case ARM::VST2q8PseudoWB_fixed: in ExpandMI()
1504 case ARM::VST2q16PseudoWB_fixed: in ExpandMI()
1505 case ARM::VST2q32PseudoWB_fixed: in ExpandMI()
1506 case ARM::VST2q8PseudoWB_register: in ExpandMI()
1507 case ARM::VST2q16PseudoWB_register: in ExpandMI()
1508 case ARM::VST2q32PseudoWB_register: in ExpandMI()
1509 case ARM::VST3d8Pseudo: in ExpandMI()
1510 case ARM::VST3d16Pseudo: in ExpandMI()
1511 case ARM::VST3d32Pseudo: in ExpandMI()
1512 case ARM::VST1d64TPseudo: in ExpandMI()
1513 case ARM::VST3d8Pseudo_UPD: in ExpandMI()
1514 case ARM::VST3d16Pseudo_UPD: in ExpandMI()
1515 case ARM::VST3d32Pseudo_UPD: in ExpandMI()
1516 case ARM::VST1d64TPseudoWB_fixed: in ExpandMI()
1517 case ARM::VST1d64TPseudoWB_register: in ExpandMI()
1518 case ARM::VST3q8Pseudo_UPD: in ExpandMI()
1519 case ARM::VST3q16Pseudo_UPD: in ExpandMI()
1520 case ARM::VST3q32Pseudo_UPD: in ExpandMI()
1521 case ARM::VST3q8oddPseudo: in ExpandMI()
1522 case ARM::VST3q16oddPseudo: in ExpandMI()
1523 case ARM::VST3q32oddPseudo: in ExpandMI()
1524 case ARM::VST3q8oddPseudo_UPD: in ExpandMI()
1525 case ARM::VST3q16oddPseudo_UPD: in ExpandMI()
1526 case ARM::VST3q32oddPseudo_UPD: in ExpandMI()
1527 case ARM::VST4d8Pseudo: in ExpandMI()
1528 case ARM::VST4d16Pseudo: in ExpandMI()
1529 case ARM::VST4d32Pseudo: in ExpandMI()
1530 case ARM::VST1d64QPseudo: in ExpandMI()
1531 case ARM::VST4d8Pseudo_UPD: in ExpandMI()
1532 case ARM::VST4d16Pseudo_UPD: in ExpandMI()
1533 case ARM::VST4d32Pseudo_UPD: in ExpandMI()
1534 case ARM::VST1d64QPseudoWB_fixed: in ExpandMI()
1535 case ARM::VST1d64QPseudoWB_register: in ExpandMI()
1536 case ARM::VST4q8Pseudo_UPD: in ExpandMI()
1537 case ARM::VST4q16Pseudo_UPD: in ExpandMI()
1538 case ARM::VST4q32Pseudo_UPD: in ExpandMI()
1539 case ARM::VST4q8oddPseudo: in ExpandMI()
1540 case ARM::VST4q16oddPseudo: in ExpandMI()
1541 case ARM::VST4q32oddPseudo: in ExpandMI()
1542 case ARM::VST4q8oddPseudo_UPD: in ExpandMI()
1543 case ARM::VST4q16oddPseudo_UPD: in ExpandMI()
1544 case ARM::VST4q32oddPseudo_UPD: in ExpandMI()
1548 case ARM::VLD1LNq8Pseudo: in ExpandMI()
1549 case ARM::VLD1LNq16Pseudo: in ExpandMI()
1550 case ARM::VLD1LNq32Pseudo: in ExpandMI()
1551 case ARM::VLD1LNq8Pseudo_UPD: in ExpandMI()
1552 case ARM::VLD1LNq16Pseudo_UPD: in ExpandMI()
1553 case ARM::VLD1LNq32Pseudo_UPD: in ExpandMI()
1554 case ARM::VLD2LNd8Pseudo: in ExpandMI()
1555 case ARM::VLD2LNd16Pseudo: in ExpandMI()
1556 case ARM::VLD2LNd32Pseudo: in ExpandMI()
1557 case ARM::VLD2LNq16Pseudo: in ExpandMI()
1558 case ARM::VLD2LNq32Pseudo: in ExpandMI()
1559 case ARM::VLD2LNd8Pseudo_UPD: in ExpandMI()
1560 case ARM::VLD2LNd16Pseudo_UPD: in ExpandMI()
1561 case ARM::VLD2LNd32Pseudo_UPD: in ExpandMI()
1562 case ARM::VLD2LNq16Pseudo_UPD: in ExpandMI()
1563 case ARM::VLD2LNq32Pseudo_UPD: in ExpandMI()
1564 case ARM::VLD3LNd8Pseudo: in ExpandMI()
1565 case ARM::VLD3LNd16Pseudo: in ExpandMI()
1566 case ARM::VLD3LNd32Pseudo: in ExpandMI()
1567 case ARM::VLD3LNq16Pseudo: in ExpandMI()
1568 case ARM::VLD3LNq32Pseudo: in ExpandMI()
1569 case ARM::VLD3LNd8Pseudo_UPD: in ExpandMI()
1570 case ARM::VLD3LNd16Pseudo_UPD: in ExpandMI()
1571 case ARM::VLD3LNd32Pseudo_UPD: in ExpandMI()
1572 case ARM::VLD3LNq16Pseudo_UPD: in ExpandMI()
1573 case ARM::VLD3LNq32Pseudo_UPD: in ExpandMI()
1574 case ARM::VLD4LNd8Pseudo: in ExpandMI()
1575 case ARM::VLD4LNd16Pseudo: in ExpandMI()
1576 case ARM::VLD4LNd32Pseudo: in ExpandMI()
1577 case ARM::VLD4LNq16Pseudo: in ExpandMI()
1578 case ARM::VLD4LNq32Pseudo: in ExpandMI()
1579 case ARM::VLD4LNd8Pseudo_UPD: in ExpandMI()
1580 case ARM::VLD4LNd16Pseudo_UPD: in ExpandMI()
1581 case ARM::VLD4LNd32Pseudo_UPD: in ExpandMI()
1582 case ARM::VLD4LNq16Pseudo_UPD: in ExpandMI()
1583 case ARM::VLD4LNq32Pseudo_UPD: in ExpandMI()
1584 case ARM::VST1LNq8Pseudo: in ExpandMI()
1585 case ARM::VST1LNq16Pseudo: in ExpandMI()
1586 case ARM::VST1LNq32Pseudo: in ExpandMI()
1587 case ARM::VST1LNq8Pseudo_UPD: in ExpandMI()
1588 case ARM::VST1LNq16Pseudo_UPD: in ExpandMI()
1589 case ARM::VST1LNq32Pseudo_UPD: in ExpandMI()
1590 case ARM::VST2LNd8Pseudo: in ExpandMI()
1591 case ARM::VST2LNd16Pseudo: in ExpandMI()
1592 case ARM::VST2LNd32Pseudo: in ExpandMI()
1593 case ARM::VST2LNq16Pseudo: in ExpandMI()
1594 case ARM::VST2LNq32Pseudo: in ExpandMI()
1595 case ARM::VST2LNd8Pseudo_UPD: in ExpandMI()
1596 case ARM::VST2LNd16Pseudo_UPD: in ExpandMI()
1597 case ARM::VST2LNd32Pseudo_UPD: in ExpandMI()
1598 case ARM::VST2LNq16Pseudo_UPD: in ExpandMI()
1599 case ARM::VST2LNq32Pseudo_UPD: in ExpandMI()
1600 case ARM::VST3LNd8Pseudo: in ExpandMI()
1601 case ARM::VST3LNd16Pseudo: in ExpandMI()
1602 case ARM::VST3LNd32Pseudo: in ExpandMI()
1603 case ARM::VST3LNq16Pseudo: in ExpandMI()
1604 case ARM::VST3LNq32Pseudo: in ExpandMI()
1605 case ARM::VST3LNd8Pseudo_UPD: in ExpandMI()
1606 case ARM::VST3LNd16Pseudo_UPD: in ExpandMI()
1607 case ARM::VST3LNd32Pseudo_UPD: in ExpandMI()
1608 case ARM::VST3LNq16Pseudo_UPD: in ExpandMI()
1609 case ARM::VST3LNq32Pseudo_UPD: in ExpandMI()
1610 case ARM::VST4LNd8Pseudo: in ExpandMI()
1611 case ARM::VST4LNd16Pseudo: in ExpandMI()
1612 case ARM::VST4LNd32Pseudo: in ExpandMI()
1613 case ARM::VST4LNq16Pseudo: in ExpandMI()
1614 case ARM::VST4LNq32Pseudo: in ExpandMI()
1615 case ARM::VST4LNd8Pseudo_UPD: in ExpandMI()
1616 case ARM::VST4LNd16Pseudo_UPD: in ExpandMI()
1617 case ARM::VST4LNd32Pseudo_UPD: in ExpandMI()
1618 case ARM::VST4LNq16Pseudo_UPD: in ExpandMI()
1619 case ARM::VST4LNq32Pseudo_UPD: in ExpandMI()
1623 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; in ExpandMI()
1624 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; in ExpandMI()
1625 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; in ExpandMI()
1626 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; in ExpandMI()
1628 case ARM::CMP_SWAP_8: in ExpandMI()
1630 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, in ExpandMI()
1631 ARM::tUXTB, NextMBBI); in ExpandMI()
1633 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, in ExpandMI()
1634 ARM::UXTB, NextMBBI); in ExpandMI()
1635 case ARM::CMP_SWAP_16: in ExpandMI()
1637 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, in ExpandMI()
1638 ARM::tUXTH, NextMBBI); in ExpandMI()
1640 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, in ExpandMI()
1641 ARM::UXTH, NextMBBI); in ExpandMI()
1642 case ARM::CMP_SWAP_32: in ExpandMI()
1644 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, in ExpandMI()
1647 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); in ExpandMI()
1649 case ARM::CMP_SWAP_64: in ExpandMI()