Lines Matching refs:Desired
774 MachineOperand &Desired = MI.getOperand(3); in ExpandCMP_SWAP() local
793 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), Desired.getReg()) in ExpandCMP_SWAP()
794 .addReg(Desired.getReg(), RegState::Kill); in ExpandCMP_SWAP()
806 LoadCmpBB->addLiveIn(Desired.getReg()); in ExpandCMP_SWAP()
819 .addOperand(Desired)); in ExpandCMP_SWAP()
891 MachineOperand &Desired = MI.getOperand(3); in ExpandCMP_SWAP_64() local
896 unsigned DesiredLo = TRI->getSubReg(Desired.getReg(), ARM::gsub_0); in ExpandCMP_SWAP_64()
897 unsigned DesiredHi = TRI->getSubReg(Desired.getReg(), ARM::gsub_1); in ExpandCMP_SWAP_64()
920 LoadCmpBB->addLiveIn(Desired.getReg()); in ExpandCMP_SWAP_64()
933 .addReg(DesiredLo, getKillRegState(Desired.isDead()))); in ExpandCMP_SWAP_64()
939 .addReg(DesiredHi, getKillRegState(Desired.isDead())); in ExpandCMP_SWAP_64()