Lines Matching refs:ResultReg
165 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
281 unsigned ResultReg = createResultReg(RC); in fastEmitInst_r() local
289 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
294 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_r()
297 return ResultReg; in fastEmitInst_r()
304 unsigned ResultReg = createResultReg(RC); in fastEmitInst_rr() local
314 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rr()
322 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_rr()
325 return ResultReg; in fastEmitInst_rr()
332 unsigned ResultReg = createResultReg(RC); in fastEmitInst_ri() local
340 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_ri()
348 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_ri()
351 return ResultReg; in fastEmitInst_ri()
359 unsigned ResultReg = createResultReg(RC); in fastEmitInst_rri() local
368 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rri()
378 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_rri()
381 return ResultReg; in fastEmitInst_rri()
387 unsigned ResultReg = createResultReg(RC); in fastEmitInst_i() local
392 ResultReg).addImm(Imm)); in fastEmitInst_i()
397 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_i()
400 return ResultReg; in fastEmitInst_i()
507 unsigned ResultReg = 0; in ARMMaterializeInt() local
509 ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); in ARMMaterializeInt()
511 if (ResultReg) in ARMMaterializeInt()
512 return ResultReg; in ARMMaterializeInt()
525 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
528 TII.get(ARM::t2LDRpci), ResultReg) in ARMMaterializeInt()
532 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
534 TII.get(ARM::LDRcp), ResultReg) in ARMMaterializeInt()
538 return ResultReg; in ARMMaterializeInt()
680 unsigned ResultReg = createResultReg(RC); in fastMaterializeAlloca() local
681 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
684 TII.get(Opc), ResultReg) in fastMaterializeAlloca()
687 return ResultReg; in fastMaterializeAlloca()
855 unsigned ResultReg = createResultReg(RC); in ARMSimplifyAddress() local
858 TII.get(Opc), ResultReg) in ARMSimplifyAddress()
861 Addr.Base.Reg = ResultReg; in ARMSimplifyAddress()
919 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, in ARMEmitLoad() argument
1003 ResultReg = createResultReg(RC); in ARMEmitLoad()
1004 assert (ResultReg > 255 && "Expected an allocated virtual register."); in ARMEmitLoad()
1006 TII.get(Opc), ResultReg); in ARMEmitLoad()
1015 .addReg(ResultReg)); in ARMEmitLoad()
1016 ResultReg = MoveReg; in ARMEmitLoad()
1050 unsigned ResultReg; in SelectLoad() local
1051 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment())) in SelectLoad()
1053 updateValueMap(I, ResultReg); in SelectLoad()
1571 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP() local
1573 TII.get(Opc), ResultReg).addReg(FP)); in SelectIToFP()
1574 updateValueMap(I, ResultReg); in SelectIToFP()
1597 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); in SelectFPToI() local
1599 TII.get(Opc), ResultReg).addReg(Op)); in SelectFPToI()
1603 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
1663 unsigned ResultReg = createResultReg(RC); in SelectSelect() local
1668 ResultReg) in SelectSelect()
1676 ResultReg) in SelectSelect()
1682 updateValueMap(I, ResultReg); in SelectSelect()
1766 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); in SelectBinaryIntOp() local
1770 TII.get(Opc), ResultReg) in SelectBinaryIntOp()
1772 updateValueMap(I, ResultReg); in SelectBinaryIntOp()
1814 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp() local
1816 TII.get(Opc), ResultReg) in SelectBinaryFPOp()
1818 updateValueMap(I, ResultReg); in SelectBinaryFPOp()
2037 unsigned ResultReg = createResultReg(DstRC); in FinishCall() local
2039 TII.get(ARM::VMOVDRR), ResultReg) in FinishCall()
2047 updateValueMap(I, ResultReg); in FinishCall()
2058 unsigned ResultReg = createResultReg(DstRC); in FinishCall() local
2061 ResultReg).addReg(RVLocs[0].getLocReg()); in FinishCall()
2065 updateValueMap(I, ResultReg); in FinishCall()
2455 unsigned ResultReg; in ARMTryEmitSmallMemCpy() local
2456 RV = ARMEmitLoad(VT, ResultReg, Src); in ARMTryEmitSmallMemCpy()
2458 RV = ARMEmitStore(VT, ResultReg, Dest); in ARMTryEmitSmallMemCpy()
2684 unsigned ResultReg; in ARMEmitIntExt() local
2700 ResultReg = createResultReg(RC); in ARMEmitIntExt()
2707 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg); in ARMEmitIntExt()
2715 SrcReg = ResultReg; in ARMEmitIntExt()
2718 return ResultReg; in ARMEmitIntExt()
2740 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt); in SelectIntExt() local
2741 if (ResultReg == 0) return false; in SelectIntExt()
2742 updateValueMap(I, ResultReg); in SelectIntExt()
2782 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); in SelectShift() local
2783 if(ResultReg == 0) return false; in SelectShift()
2786 TII.get(Opc), ResultReg) in SelectShift()
2797 updateValueMap(I, ResultReg); in SelectShift()
2927 unsigned ResultReg = MI->getOperand(0).getReg(); in tryToFoldLoadIntoMI() local
2928 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false)) in tryToFoldLoadIntoMI()
3048 unsigned ResultReg = createResultReg(RC); in fastLowerArguments() local
3051 ResultReg).addReg(DstReg, getKillRegState(true)); in fastLowerArguments()
3052 updateValueMap(&*I, ResultReg); in fastLowerArguments()