Lines Matching refs:is64BitVector
269 bool is64BitVector);
1688 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1690 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1822 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
1823 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVLD()
1850 if (!is64BitVector) in SelectVLD()
1866 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
1867 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
1934 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
1962 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
1963 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVST()
1995 if (is64BitVector || NumVecs <= 2) { in SelectVST()
1999 } else if (is64BitVector) { in SelectVST()
2021 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVST()
2112 bool is64BitVector = VT.is64BitVector(); in SelectVLDSTLane() local
2146 if (!is64BitVector) in SelectVLDSTLane()
2170 if (is64BitVector) in SelectVLDSTLane()
2179 if (is64BitVector) in SelectVLDSTLane()
2190 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLDSTLane()
2204 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDSTLane()