Lines Matching refs:b0001
1001 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
1002 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
1003 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
1004 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
1005 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
1006 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
1144 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1180 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
2003 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
2004 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
2005 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
2006 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
2007 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
2008 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
2140 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
2178 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
4134 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
4135 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
4144 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
4147 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
4314 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
4317 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
4320 def VMLAslhd : N3VDMulOpSL16<0b01, 0b0001, IIC_VMACD, "vmla", "f16",
4323 def VMLAslhq : N3VQMulOpSL16<0b01, 0b0001, IIC_VMACQ, "vmla", "f16",
4848 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4850 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4854 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4856 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4860 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4862 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4904 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4909 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4953 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4958 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
5010 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5047 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5087 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
5092 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
5101 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
5106 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
5537 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
5538 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;