Lines Matching refs:b1011

1296 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1309 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1337 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1349 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
2290 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2303 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2329 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2341 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
4230 defm VQDMULH  : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4252 defm VQRDMULH   : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
4292 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
4366   defm VQRDMLAH : N3VInt3_HS<1, 0, 0b1011, 1, IIC_VMACi16D, IIC_VMACi32D,
4592 defm VQDMLSL  : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
5266 def  VPADDi8  : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
5269 def  VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
5272 def  VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
5803 def VGETLNs8  : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
5811 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
5819 def VGETLNu8  : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
5827 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
5835 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
5888 def VSETLNi8  : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
5896 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
5904 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
5977   : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
5981   : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
6457   : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
6487   : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),