Lines Matching refs:Rt2
1279 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1281 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1449 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1450 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1557 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1559 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1564 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1566 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1571 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1572 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1579 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1581 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
3302 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
3305 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3308 bits<4> Rt2;
3309 let Inst{11-8} = Rt2;
3336 def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2),
3339 "ldaexd", "\t$Rt, $Rt2, $addr", "",
3342 bits<4> Rt2;
3343 let Inst{11-8} = Rt2;
3384 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3386 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3389 bits<4> Rt2;
3390 let Inst{11-8} = Rt2;
3429 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3431 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3434 bits<4> Rt2;
3435 let Inst{11-8} = Rt2;
4174 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4180 bits<4> Rt2;
4186 let Inst{19-16} = Rt2;
4240 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4242 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4245 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4248 GPR:$Rt2, imm:$CRm)]> {
4253 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1, (outs GPR:$Rt, GPR:$Rt2),
4256 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1, (outs GPR:$Rt, GPR:$Rt2),