Lines Matching refs:Dm
337 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
338 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
339 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
359 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
360 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
361 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
381 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
382 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
383 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
399 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
400 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
401 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
420 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
421 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
422 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
454 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
455 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
456 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
482 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
483 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
484 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
502 (outs), (ins DPR:$Dd, DPR:$Dm),
503 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
504 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
523 (outs), (ins DPR:$Dd, DPR:$Dm),
524 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
547 (outs DPR:$Dd), (ins DPR:$Dm),
548 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
549 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
642 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
643 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
644 [(set SPR:$Sd, (fround DPR:$Dm))]> {
647 bits<5> Dm;
650 let Inst{3-0} = Dm{3-0};
651 let Inst{5} = Dm{4};
700 (outs SPR:$Sd), (ins DPR:$Dm),
701 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
705 bits<5> Dm;
708 let Inst{3-0} = Dm{3-0};
709 let Inst{5} = Dm{4};
727 (outs SPR:$Sd), (ins DPR:$Dm),
728 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
732 bits<5> Dm;
737 let Inst{3-0} = Dm{3-0};
738 let Inst{5} = Dm{4};
789 (outs SPR:$Sd), (ins DPR:$Dm),
790 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
793 bits<5> Dm;
798 let Inst{3-0} = Dm{3-0};
799 let Inst{5} = Dm{4};
804 (outs SPR:$Sd), (ins DPR:$Dm),
805 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
808 bits<5> Dm;
813 let Inst{3-0} = Dm{3-0};
814 let Inst{5} = Dm{4};
847 (outs DPR:$Dd), (ins DPR:$Dm),
848 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
849 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
884 (outs DPR:$Dd), (ins DPR:$Dm),
885 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
886 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
898 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
899 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p), 0>,
925 (outs DPR:$Dd), (ins DPR:$Dm),
926 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
927 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
936 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
937 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm), 0>,
947 (outs DPR:$Dd), (ins DPR:$Dm),
948 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
949 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
963 (outs DPR:$Dd), (ins DPR:$Dm),
964 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
1033 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
1034 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
1037 bits<5> Dm;
1042 let Inst{3-0} = Dm{3-0};
1043 let Inst{5} = Dm{4};
1054 // $Rt = EXTRACT_SUBREG $Dm, ssub_0
1055 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
1086 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
1087 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
1088 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
1090 bits<5> Dm;
1095 let Inst{3-0} = Dm{3-0};
1096 let Inst{5} = Dm{4};
1107 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1
1342 bits<5> Dm;
1345 let Inst{3-0} = Dm{3-0};
1346 let Inst{5} = Dm{4};
1391 (outs SPR:$Sd), (ins DPR:$Dm),
1392 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1431 (outs SPR:$Sd), (ins DPR:$Dm),
1432 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1474 (outs SPR:$Sd), (ins DPR:$Dm),
1475 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1476 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1495 (outs SPR:$Sd), (ins DPR:$Dm),
1496 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1497 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1698 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1699 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1700 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1732 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1733 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
1734 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1766 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1767 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1768 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1800 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1801 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1802 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1836 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1837 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1838 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1870 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1871 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1878 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1879 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1880 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1912 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1913 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1919 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1920 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1927 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1928 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1929 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1961 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1962 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1968 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1969 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1976 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1977 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1978 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
2010 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
2011 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2017 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
2018 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2024 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
2025 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2036 def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
2039 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
2254 def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm",
2255 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
2258 def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm",
2259 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
2263 def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;