114                                   const DebugLoc &DL, unsigned DestReg,  in copyPhysReg()  argument
117   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
118     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);  in copyPhysReg()
120   AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)  in copyPhysReg()
169                      unsigned DestReg, int FI,  in loadRegFromStackSlot()  argument
183     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)  in loadRegFromStackSlot()
192     if (TargetRegisterInfo::isVirtualRegister(DestReg)) {  in loadRegFromStackSlot()
194       MRI->constrainRegClass(DestReg,  in loadRegFromStackSlot()
199     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
200     AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
204     if (TargetRegisterInfo::isPhysicalRegister(DestReg))  in loadRegFromStackSlot()
205       MIB.addReg(DestReg, RegState::ImplicitDefine);  in loadRegFromStackSlot()
209   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);  in loadRegFromStackSlot()
223                                   const DebugLoc &dl, unsigned DestReg,  in emitT2RegPlusImmediate()  argument
228   if (NumBytes == 0 && DestReg != BaseReg) {  in emitT2RegPlusImmediate()
229     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)  in emitT2RegPlusImmediate()
240   if (DestReg != ARM::SP && DestReg != BaseReg &&  in emitT2RegPlusImmediate()
246       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)  in emitT2RegPlusImmediate()
252       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)  in emitT2RegPlusImmediate()
253         .addReg(DestReg)  in emitT2RegPlusImmediate()
261         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)  in emitT2RegPlusImmediate()
263           .addReg(DestReg, RegState::Kill)  in emitT2RegPlusImmediate()
272         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)  in emitT2RegPlusImmediate()
274           .addReg(DestReg, RegState::Kill)  in emitT2RegPlusImmediate()
285     if (DestReg == ARM::SP && BaseReg != ARM::SP) {  in emitT2RegPlusImmediate()
287       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)  in emitT2RegPlusImmediate()
296       if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {  in emitT2RegPlusImmediate()
299         AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)  in emitT2RegPlusImmediate()
318       assert(DestReg != ARM::SP && BaseReg != ARM::SP);  in emitT2RegPlusImmediate()
338       AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)  in emitT2RegPlusImmediate()
344     BaseReg = DestReg;  in emitT2RegPlusImmediate()