Lines Matching refs:Hexagon
72 assert(Hexagon::IntRegsRegClass.contains(Reg)); in getHexagonRegisterPair()
75 assert(Hexagon::DoubleRegsRegClass.contains(Pair)); in getHexagonRegisterPair()
264 case Hexagon::A2_iconst: { in HexagonProcessInstruction()
265 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction()
272 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
278 case Hexagon::CONST64_Float_Real: in HexagonProcessInstruction()
279 case Hexagon::CONST64_Int_Real: in HexagonProcessInstruction()
289 TmpInst.setOpcode(Hexagon::L2_loadrdgp); in HexagonProcessInstruction()
297 case Hexagon::CONST32: in HexagonProcessInstruction()
298 case Hexagon::CONST32_Float_Real: in HexagonProcessInstruction()
299 case Hexagon::CONST32_Int_Real: in HexagonProcessInstruction()
300 case Hexagon::FCONST32_nsdata: in HexagonProcessInstruction()
308 TmpInst.setOpcode(Hexagon::L2_loadrigp); in HexagonProcessInstruction()
319 case Hexagon::C2_pxfer_map: { in HexagonProcessInstruction()
321 MappedInst.setOpcode(Hexagon::C2_or); in HexagonProcessInstruction()
329 case Hexagon::M2_vrcmpys_acc_s1: { in HexagonProcessInstruction()
334 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h); in HexagonProcessInstruction()
336 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l); in HexagonProcessInstruction()
340 case Hexagon::M2_vrcmpys_s1: { in HexagonProcessInstruction()
345 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h); in HexagonProcessInstruction()
347 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l); in HexagonProcessInstruction()
352 case Hexagon::M2_vrcmpys_s1rp: { in HexagonProcessInstruction()
357 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h); in HexagonProcessInstruction()
359 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l); in HexagonProcessInstruction()
364 case Hexagon::A4_boundscheck: { in HexagonProcessInstruction()
369 MappedInst.setOpcode(Hexagon::A4_boundscheck_hi); in HexagonProcessInstruction()
371 MappedInst.setOpcode(Hexagon::A4_boundscheck_lo); in HexagonProcessInstruction()
375 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: { in HexagonProcessInstruction()
384 TmpInst.setOpcode(Hexagon::S2_vsathub); in HexagonProcessInstruction()
390 TmpInst.setOpcode(Hexagon::S5_asrhub_rnd_sat); in HexagonProcessInstruction()
400 case Hexagon::S5_vasrhrnd_goodsyntax: in HexagonProcessInstruction()
401 case Hexagon::S2_asr_i_p_rnd_goodsyntax: { in HexagonProcessInstruction()
410 TmpInst.setOpcode(Hexagon::A2_combinew); in HexagonProcessInstruction()
413 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction()
414 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction()
422 if (Inst.getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax) in HexagonProcessInstruction()
423 TmpInst.setOpcode(Hexagon::S2_asr_i_p_rnd); in HexagonProcessInstruction()
425 TmpInst.setOpcode(Hexagon::S5_vasrhrnd); in HexagonProcessInstruction()
436 case Hexagon::S2_asr_i_r_rnd_goodsyntax: { in HexagonProcessInstruction()
445 TmpInst.setOpcode(Hexagon::A2_tfr); in HexagonProcessInstruction()
451 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd); in HexagonProcessInstruction()
461 case Hexagon::TFRI_f: in HexagonProcessInstruction()
462 MappedInst.setOpcode(Hexagon::A2_tfrsi); in HexagonProcessInstruction()
464 case Hexagon::TFRI_cPt_f: in HexagonProcessInstruction()
465 MappedInst.setOpcode(Hexagon::C2_cmoveit); in HexagonProcessInstruction()
467 case Hexagon::TFRI_cNotPt_f: in HexagonProcessInstruction()
468 MappedInst.setOpcode(Hexagon::C2_cmoveif); in HexagonProcessInstruction()
470 case Hexagon::MUX_ri_f: in HexagonProcessInstruction()
471 MappedInst.setOpcode(Hexagon::C2_muxri); in HexagonProcessInstruction()
473 case Hexagon::MUX_ir_f: in HexagonProcessInstruction()
474 MappedInst.setOpcode(Hexagon::C2_muxir); in HexagonProcessInstruction()
478 case Hexagon::A2_tfrpi: { in HexagonProcessInstruction()
483 TmpInst.setOpcode(Hexagon::A2_combineii); in HexagonProcessInstruction()
499 case Hexagon::A2_tfrp: { in HexagonProcessInstruction()
501 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction()
502 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction()
506 MappedInst.setOpcode(Hexagon::A2_combinew); in HexagonProcessInstruction()
510 case Hexagon::A2_tfrpt: in HexagonProcessInstruction()
511 case Hexagon::A2_tfrpf: { in HexagonProcessInstruction()
513 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction()
514 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction()
518 MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt) in HexagonProcessInstruction()
519 ? Hexagon::C2_ccombinewt in HexagonProcessInstruction()
520 : Hexagon::C2_ccombinewf); in HexagonProcessInstruction()
523 case Hexagon::A2_tfrptnew: in HexagonProcessInstruction()
524 case Hexagon::A2_tfrpfnew: { in HexagonProcessInstruction()
526 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction()
527 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction()
531 MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew) in HexagonProcessInstruction()
532 ? Hexagon::C2_ccombinewnewt in HexagonProcessInstruction()
533 : Hexagon::C2_ccombinewnewf); in HexagonProcessInstruction()
537 case Hexagon::M2_mpysmi: { in HexagonProcessInstruction()
545 MappedInst.setOpcode(Hexagon::M2_mpysin); in HexagonProcessInstruction()
549 MappedInst.setOpcode(Hexagon::M2_mpysip); in HexagonProcessInstruction()
553 case Hexagon::A2_addsp: { in HexagonProcessInstruction()
558 MappedInst.setOpcode(Hexagon::A2_addsph); in HexagonProcessInstruction()
560 MappedInst.setOpcode(Hexagon::A2_addspl); in HexagonProcessInstruction()
564 case Hexagon::HEXAGON_V6_vd0_pseudo: in HexagonProcessInstruction()
565 case Hexagon::HEXAGON_V6_vd0_pseudo_128B: { in HexagonProcessInstruction()
570 TmpInst.setOpcode(Hexagon::V6_vxor); in HexagonProcessInstruction()