204       LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) {  in CC_Hexagon_VarArg()
349        LocVT == MVT::v128i8)) {  in CC_HexagonVector()
372        LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) {  in CC_HexagonVector()
418   } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 ||  in RetCC_Hexagon()
546           ty == MVT::v128i8 ||  in IsHvxVectorType()
899                               VT == MVT::v64i16 || VT == MVT::v128i8);  in getIndexedAddressParts()
1126                  RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {  in LowerFormalArguments()
1134                   RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) {  in LowerFormalArguments()
1759       addRegisterClass(MVT::v128i8, &Hexagon::VecDblRegsRegClass);  in HexagonTargetLowering()
1765       addRegisterClass(MVT::v128i8,  &Hexagon::VectorRegs128BRegClass);  in HexagonTargetLowering()
1999       setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8,  Custom);  in HexagonTargetLowering()
2072     for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) {  in HexagonTargetLowering()
2891        case MVT::v128i8:  in getRegForInlineAsmConstraint()
3029   case MVT::v128i8:  in allowsMisalignedMemoryAccesses()
3061   case MVT::v128i8:  in findRepresentativeClass()