Lines Matching refs:v16i64
203 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_Hexagon_VarArg()
348 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
371 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
419 LocVT == MVT::v32i32 || LocVT == MVT::v16i64 || in RetCC_Hexagon()
545 ty == MVT::v16i64 || ty == MVT::v32i32 || ty == MVT::v64i16 || in IsHvxVectorType()
898 (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 || in getIndexedAddressParts()
1125 ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || in LowerFormalArguments()
1133 } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || in LowerFormalArguments()
1762 addRegisterClass(MVT::v16i64, &Hexagon::VecDblRegsRegClass); in HexagonTargetLowering()
1768 addRegisterClass(MVT::v16i64, &Hexagon::VectorRegs128BRegClass); in HexagonTargetLowering()
2002 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i64, Custom); in HexagonTargetLowering()
2072 for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) { in HexagonTargetLowering()
2890 case MVT::v16i64: in getRegForInlineAsmConstraint()
3038 case MVT::v16i64: in allowsMisalignedMemoryAccesses()
3064 case MVT::v16i64: in findRepresentativeClass()