Lines Matching refs:Hexagon
104 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), in HexagonInstrInfo()
109 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
110 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
115 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_loreg)) && in isDblRegForSubInst()
116 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_hireg)); in isDblRegForSubInst()
140 if (EndLoopOp == Hexagon::ENDLOOP0) { in findLoopInstr()
141 LOOPi = Hexagon::J2_loop0i; in findLoopInstr()
142 LOOPr = Hexagon::J2_loop0r; in findLoopInstr()
144 LOOPi = Hexagon::J2_loop1i; in findLoopInstr()
145 LOOPr = Hexagon::J2_loop1r; in findLoopInstr()
239 case Hexagon::L2_loadrb_io: in isLoadFromStackSlot()
240 case Hexagon::L2_loadrub_io: in isLoadFromStackSlot()
241 case Hexagon::L2_loadrh_io: in isLoadFromStackSlot()
242 case Hexagon::L2_loadruh_io: in isLoadFromStackSlot()
243 case Hexagon::L2_loadri_io: in isLoadFromStackSlot()
244 case Hexagon::L2_loadrd_io: in isLoadFromStackSlot()
245 case Hexagon::V6_vL32b_ai: in isLoadFromStackSlot()
246 case Hexagon::V6_vL32b_ai_128B: in isLoadFromStackSlot()
247 case Hexagon::V6_vL32Ub_ai: in isLoadFromStackSlot()
248 case Hexagon::V6_vL32Ub_ai_128B: in isLoadFromStackSlot()
249 case Hexagon::LDriw_pred: in isLoadFromStackSlot()
250 case Hexagon::LDriw_mod: in isLoadFromStackSlot()
251 case Hexagon::LDriq_pred_V6: in isLoadFromStackSlot()
252 case Hexagon::LDriq_pred_vec_V6: in isLoadFromStackSlot()
253 case Hexagon::LDriv_pseudo_V6: in isLoadFromStackSlot()
254 case Hexagon::LDrivv_pseudo_V6: in isLoadFromStackSlot()
255 case Hexagon::LDriq_pred_V6_128B: in isLoadFromStackSlot()
256 case Hexagon::LDriq_pred_vec_V6_128B: in isLoadFromStackSlot()
257 case Hexagon::LDriv_pseudo_V6_128B: in isLoadFromStackSlot()
258 case Hexagon::LDrivv_pseudo_V6_128B: { in isLoadFromStackSlot()
269 case Hexagon::L2_ploadrbt_io: in isLoadFromStackSlot()
270 case Hexagon::L2_ploadrbf_io: in isLoadFromStackSlot()
271 case Hexagon::L2_ploadrubt_io: in isLoadFromStackSlot()
272 case Hexagon::L2_ploadrubf_io: in isLoadFromStackSlot()
273 case Hexagon::L2_ploadrht_io: in isLoadFromStackSlot()
274 case Hexagon::L2_ploadrhf_io: in isLoadFromStackSlot()
275 case Hexagon::L2_ploadruht_io: in isLoadFromStackSlot()
276 case Hexagon::L2_ploadruhf_io: in isLoadFromStackSlot()
277 case Hexagon::L2_ploadrit_io: in isLoadFromStackSlot()
278 case Hexagon::L2_ploadrif_io: in isLoadFromStackSlot()
279 case Hexagon::L2_ploadrdt_io: in isLoadFromStackSlot()
280 case Hexagon::L2_ploadrdf_io: { in isLoadFromStackSlot()
306 case Hexagon::S2_storerb_io: in isStoreToStackSlot()
307 case Hexagon::S2_storerh_io: in isStoreToStackSlot()
308 case Hexagon::S2_storeri_io: in isStoreToStackSlot()
309 case Hexagon::S2_storerd_io: in isStoreToStackSlot()
310 case Hexagon::V6_vS32b_ai: in isStoreToStackSlot()
311 case Hexagon::V6_vS32b_ai_128B: in isStoreToStackSlot()
312 case Hexagon::V6_vS32Ub_ai: in isStoreToStackSlot()
313 case Hexagon::V6_vS32Ub_ai_128B: in isStoreToStackSlot()
314 case Hexagon::STriw_pred: in isStoreToStackSlot()
315 case Hexagon::STriw_mod: in isStoreToStackSlot()
316 case Hexagon::STriq_pred_V6: in isStoreToStackSlot()
317 case Hexagon::STriq_pred_vec_V6: in isStoreToStackSlot()
318 case Hexagon::STriv_pseudo_V6: in isStoreToStackSlot()
319 case Hexagon::STrivv_pseudo_V6: in isStoreToStackSlot()
320 case Hexagon::STriq_pred_V6_128B: in isStoreToStackSlot()
321 case Hexagon::STriq_pred_vec_V6_128B: in isStoreToStackSlot()
322 case Hexagon::STriv_pseudo_V6_128B: in isStoreToStackSlot()
323 case Hexagon::STrivv_pseudo_V6_128B: { in isStoreToStackSlot()
334 case Hexagon::S2_pstorerbt_io: in isStoreToStackSlot()
335 case Hexagon::S2_pstorerbf_io: in isStoreToStackSlot()
336 case Hexagon::S2_pstorerht_io: in isStoreToStackSlot()
337 case Hexagon::S2_pstorerhf_io: in isStoreToStackSlot()
338 case Hexagon::S2_pstorerit_io: in isStoreToStackSlot()
339 case Hexagon::S2_pstorerif_io: in isStoreToStackSlot()
340 case Hexagon::S2_pstorerdt_io: in isStoreToStackSlot()
341 case Hexagon::S2_pstorerdf_io: { in isStoreToStackSlot()
415 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump && in analyzeBranch()
451 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB()) in analyzeBranch()
453 if (SecLastOpcode == Hexagon::J2_jump && in analyzeBranch()
465 if (LastOpcode == Hexagon::J2_jump) { in analyzeBranch()
497 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) { in analyzeBranch()
510 (LastOpcode == Hexagon::J2_jump)) { in analyzeBranch()
521 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) { in analyzeBranch()
530 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) { in analyzeBranch()
555 if (Count && (I->getOpcode() == Hexagon::J2_jump)) in RemoveBranch()
569 unsigned BOpc = Hexagon::J2_jump; in InsertBranch()
570 unsigned BccOpc = Hexagon::J2_jumpt; in InsertBranch()
700 if (Loop->getOpcode() == Hexagon::J2_loop0i || in reduceLoopCount()
701 Loop->getOpcode() == Hexagon::J2_loop1i) { in reduceLoopCount()
711 assert(Loop->getOpcode() == Hexagon::J2_loop0r && "Unexpected instruction"); in reduceLoopCount()
715 MachineInstr *NewCmp = BuildMI(&MBB, DL, get(Hexagon::C2_cmpgtui), LoopEnd). in reduceLoopCount()
718 MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount). in reduceLoopCount()
730 BuildMI(&MBB, DL, get(Hexagon::J2_loop0r)). in reduceLoopCount()
735 Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf)); in reduceLoopCount()
767 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
768 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg) in copyPhysReg()
772 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
773 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg) in copyPhysReg()
777 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
779 BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg) in copyPhysReg()
783 if (Hexagon::CtrRegsRegClass.contains(DestReg) && in copyPhysReg()
784 Hexagon::IntRegsRegClass.contains(SrcReg)) { in copyPhysReg()
785 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg) in copyPhysReg()
789 if (Hexagon::IntRegsRegClass.contains(DestReg) && in copyPhysReg()
790 Hexagon::CtrRegsRegClass.contains(SrcReg)) { in copyPhysReg()
791 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg) in copyPhysReg()
795 if (Hexagon::ModRegsRegClass.contains(DestReg) && in copyPhysReg()
796 Hexagon::IntRegsRegClass.contains(SrcReg)) { in copyPhysReg()
797 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg) in copyPhysReg()
801 if (Hexagon::PredRegsRegClass.contains(SrcReg) && in copyPhysReg()
802 Hexagon::IntRegsRegClass.contains(DestReg)) { in copyPhysReg()
803 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg) in copyPhysReg()
807 if (Hexagon::IntRegsRegClass.contains(SrcReg) && in copyPhysReg()
808 Hexagon::PredRegsRegClass.contains(DestReg)) { in copyPhysReg()
809 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg) in copyPhysReg()
813 if (Hexagon::PredRegsRegClass.contains(SrcReg) && in copyPhysReg()
814 Hexagon::IntRegsRegClass.contains(DestReg)) { in copyPhysReg()
815 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg) in copyPhysReg()
819 if (Hexagon::VectorRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
820 BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg). in copyPhysReg()
824 if (Hexagon::VecDblRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
825 BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg) in copyPhysReg()
826 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag) in copyPhysReg()
827 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag); in copyPhysReg()
830 if (Hexagon::VecPredRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
831 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg) in copyPhysReg()
836 if (Hexagon::VecPredRegsRegClass.contains(SrcReg) && in copyPhysReg()
837 Hexagon::VectorRegsRegClass.contains(DestReg)) { in copyPhysReg()
841 if (Hexagon::VecPredRegsRegClass.contains(DestReg) && in copyPhysReg()
842 Hexagon::VectorRegsRegClass.contains(SrcReg)) { in copyPhysReg()
846 if (Hexagon::VecPredRegs128BRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
847 unsigned DstHi = HRI.getSubReg(DestReg, Hexagon::subreg_hireg); in copyPhysReg()
848 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DstHi) in copyPhysReg()
849 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag); in copyPhysReg()
850 unsigned DstLo = HRI.getSubReg(DestReg, Hexagon::subreg_loreg); in copyPhysReg()
851 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DstLo) in copyPhysReg()
852 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag); in copyPhysReg()
879 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
880 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io)) in storeRegToStackSlot()
883 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
884 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io)) in storeRegToStackSlot()
887 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
888 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred)) in storeRegToStackSlot()
891 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
892 BuildMI(MBB, I, DL, get(Hexagon::STriw_mod)) in storeRegToStackSlot()
895 } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
896 BuildMI(MBB, I, DL, get(Hexagon::STriq_pred_V6_128B)) in storeRegToStackSlot()
899 } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
900 BuildMI(MBB, I, DL, get(Hexagon::STriq_pred_V6)) in storeRegToStackSlot()
903 } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
905 BuildMI(MBB, I, DL, get(Hexagon::STriv_pseudo_V6_128B)) in storeRegToStackSlot()
908 } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
910 BuildMI(MBB, I, DL, get(Hexagon::STriv_pseudo_V6)) in storeRegToStackSlot()
913 } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
915 BuildMI(MBB, I, DL, get(Hexagon::STrivv_pseudo_V6)) in storeRegToStackSlot()
918 } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
920 BuildMI(MBB, I, DL, get(Hexagon::STrivv_pseudo_V6_128B)) in storeRegToStackSlot()
941 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
942 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg) in loadRegFromStackSlot()
944 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
945 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg) in loadRegFromStackSlot()
947 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
948 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg) in loadRegFromStackSlot()
950 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
951 BuildMI(MBB, I, DL, get(Hexagon::LDriw_mod), DestReg) in loadRegFromStackSlot()
953 } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
954 BuildMI(MBB, I, DL, get(Hexagon::LDriq_pred_V6_128B), DestReg) in loadRegFromStackSlot()
956 } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
957 BuildMI(MBB, I, DL, get(Hexagon::LDriq_pred_V6), DestReg) in loadRegFromStackSlot()
959 } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
961 BuildMI(MBB, I, DL, get(Hexagon::LDrivv_pseudo_V6_128B), DestReg) in loadRegFromStackSlot()
963 } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
965 BuildMI(MBB, I, DL, get(Hexagon::LDriv_pseudo_V6_128B), DestReg) in loadRegFromStackSlot()
967 } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
969 BuildMI(MBB, I, DL, get(Hexagon::LDriv_pseudo_V6), DestReg) in loadRegFromStackSlot()
971 } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
973 BuildMI(MBB, I, DL, get(Hexagon::LDrivv_pseudo_V6), DestReg) in loadRegFromStackSlot()
1008 case Hexagon::ALIGNA: in expandPostRAPseudo()
1009 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg()) in expandPostRAPseudo()
1014 case Hexagon::HEXAGON_V6_vassignp_128B: in expandPostRAPseudo()
1015 case Hexagon::HEXAGON_V6_vassignp: { in expandPostRAPseudo()
1023 case Hexagon::HEXAGON_V6_lo_128B: in expandPostRAPseudo()
1024 case Hexagon::HEXAGON_V6_lo: { in expandPostRAPseudo()
1027 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::subreg_loreg); in expandPostRAPseudo()
1033 case Hexagon::HEXAGON_V6_hi_128B: in expandPostRAPseudo()
1034 case Hexagon::HEXAGON_V6_hi: { in expandPostRAPseudo()
1037 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::subreg_hireg); in expandPostRAPseudo()
1043 case Hexagon::STrivv_indexed_128B: in expandPostRAPseudo()
1045 case Hexagon::STrivv_indexed: { in expandPostRAPseudo()
1047 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::subreg_hireg); in expandPostRAPseudo()
1048 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::subreg_loreg); in expandPostRAPseudo()
1049 unsigned NewOpcd = Is128B ? Hexagon::V6_vS32b_ai_128B in expandPostRAPseudo()
1050 : Hexagon::V6_vS32b_ai; in expandPostRAPseudo()
1068 case Hexagon::LDrivv_pseudo_V6_128B: in expandPostRAPseudo()
1069 case Hexagon::LDrivv_indexed_128B: in expandPostRAPseudo()
1071 case Hexagon::LDrivv_pseudo_V6: in expandPostRAPseudo()
1072 case Hexagon::LDrivv_indexed: { in expandPostRAPseudo()
1073 unsigned NewOpcd = Is128B ? Hexagon::V6_vL32b_ai_128B in expandPostRAPseudo()
1074 : Hexagon::V6_vL32b_ai; in expandPostRAPseudo()
1079 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)) in expandPostRAPseudo()
1084 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)) in expandPostRAPseudo()
1092 case Hexagon::LDriv_pseudo_V6_128B: in expandPostRAPseudo()
1094 case Hexagon::LDriv_pseudo_V6: { in expandPostRAPseudo()
1096 unsigned NewOpc = Is128B ? Hexagon::V6_vL32b_ai_128B in expandPostRAPseudo()
1097 : Hexagon::V6_vL32b_ai; in expandPostRAPseudo()
1106 case Hexagon::STriv_pseudo_V6_128B: in expandPostRAPseudo()
1108 case Hexagon::STriv_pseudo_V6: { in expandPostRAPseudo()
1109 unsigned NewOpc = Is128B ? Hexagon::V6_vS32b_ai_128B in expandPostRAPseudo()
1110 : Hexagon::V6_vS32b_ai; in expandPostRAPseudo()
1120 case Hexagon::TFR_PdTrue: { in expandPostRAPseudo()
1122 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg) in expandPostRAPseudo()
1128 case Hexagon::TFR_PdFalse: { in expandPostRAPseudo()
1130 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg) in expandPostRAPseudo()
1136 case Hexagon::VMULW: { in expandPostRAPseudo()
1141 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg); in expandPostRAPseudo()
1142 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg); in expandPostRAPseudo()
1143 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg); in expandPostRAPseudo()
1144 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg); in expandPostRAPseudo()
1145 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi), in expandPostRAPseudo()
1146 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)) in expandPostRAPseudo()
1149 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi), in expandPostRAPseudo()
1150 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)) in expandPostRAPseudo()
1160 case Hexagon::VMULW_ACC: { in expandPostRAPseudo()
1166 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg); in expandPostRAPseudo()
1167 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg); in expandPostRAPseudo()
1168 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg); in expandPostRAPseudo()
1169 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg); in expandPostRAPseudo()
1170 unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::subreg_hireg); in expandPostRAPseudo()
1171 unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::subreg_loreg); in expandPostRAPseudo()
1172 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci), in expandPostRAPseudo()
1173 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)) in expandPostRAPseudo()
1177 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci), in expandPostRAPseudo()
1178 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)) in expandPostRAPseudo()
1191 case Hexagon::Insert4: { in expandPostRAPseudo()
1201 unsigned DstSubHi = HRI.getSubReg(DstReg, Hexagon::subreg_hireg); in expandPostRAPseudo()
1202 unsigned DstSubLo = HRI.getSubReg(DstReg, Hexagon::subreg_loreg); in expandPostRAPseudo()
1203 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::S2_insert), in expandPostRAPseudo()
1204 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)) in expandPostRAPseudo()
1209 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::S2_insert), in expandPostRAPseudo()
1210 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)) in expandPostRAPseudo()
1215 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::S2_insert), in expandPostRAPseudo()
1216 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)) in expandPostRAPseudo()
1221 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::S2_insert), in expandPostRAPseudo()
1222 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)) in expandPostRAPseudo()
1233 case Hexagon::MUX64_rr: { in expandPostRAPseudo()
1247 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd) in expandPostRAPseudo()
1251 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd) in expandPostRAPseudo()
1257 case Hexagon::VSelectPseudo_V6: { in expandPostRAPseudo()
1262 BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov)) in expandPostRAPseudo()
1266 BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov)) in expandPostRAPseudo()
1273 case Hexagon::VSelectDblPseudo_V6: { in expandPostRAPseudo()
1278 unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::subreg_loreg); in expandPostRAPseudo()
1279 unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::subreg_hireg); in expandPostRAPseudo()
1280 BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine)) in expandPostRAPseudo()
1285 SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::subreg_loreg); in expandPostRAPseudo()
1286 SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::subreg_hireg); in expandPostRAPseudo()
1287 BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine)) in expandPostRAPseudo()
1295 case Hexagon::TCRETURNi: in expandPostRAPseudo()
1296 MI.setDesc(get(Hexagon::J2_jump)); in expandPostRAPseudo()
1298 case Hexagon::TCRETURNr: in expandPostRAPseudo()
1299 MI.setDesc(get(Hexagon::J2_jumpr)); in expandPostRAPseudo()
1301 case Hexagon::TFRI_f: in expandPostRAPseudo()
1302 case Hexagon::TFRI_cPt_f: in expandPostRAPseudo()
1303 case Hexagon::TFRI_cNotPt_f: { in expandPostRAPseudo()
1304 unsigned Opx = (Opc == Hexagon::TFRI_f) ? 1 : 2; in expandPostRAPseudo()
1308 unsigned NewOpc = (Opc == Hexagon::TFRI_f) ? Hexagon::A2_tfrsi : in expandPostRAPseudo()
1309 (Opc == Hexagon::TFRI_cPt_f) ? Hexagon::C2_cmoveit : in expandPostRAPseudo()
1310 Hexagon::C2_cmoveif; in expandPostRAPseudo()
1342 BuildMI(MBB, MI, DL, get(Hexagon::A2_nop)); in insertNoop()
1426 if (RC == &Hexagon::PredRegsRegClass) { in DefinesPredicate()
1462 if (MI.getOpcode() == Hexagon::CALLv3nr) in isSchedulingBoundary()
1530 case Hexagon::C2_cmpeq: in analyzeCompare()
1531 case Hexagon::C2_cmpeqp: in analyzeCompare()
1532 case Hexagon::C2_cmpgt: in analyzeCompare()
1533 case Hexagon::C2_cmpgtp: in analyzeCompare()
1534 case Hexagon::C2_cmpgtu: in analyzeCompare()
1535 case Hexagon::C2_cmpgtup: in analyzeCompare()
1536 case Hexagon::C4_cmpneq: in analyzeCompare()
1537 case Hexagon::C4_cmplte: in analyzeCompare()
1538 case Hexagon::C4_cmplteu: in analyzeCompare()
1539 case Hexagon::C2_cmpeqi: in analyzeCompare()
1540 case Hexagon::C2_cmpgti: in analyzeCompare()
1541 case Hexagon::C2_cmpgtui: in analyzeCompare()
1542 case Hexagon::C4_cmpneqi: in analyzeCompare()
1543 case Hexagon::C4_cmplteui: in analyzeCompare()
1544 case Hexagon::C4_cmpltei: in analyzeCompare()
1548 case Hexagon::A4_cmpbeq: in analyzeCompare()
1549 case Hexagon::A4_cmpbgt: in analyzeCompare()
1550 case Hexagon::A4_cmpbgtu: in analyzeCompare()
1551 case Hexagon::A4_cmpbeqi: in analyzeCompare()
1552 case Hexagon::A4_cmpbgti: in analyzeCompare()
1553 case Hexagon::A4_cmpbgtui: in analyzeCompare()
1557 case Hexagon::A4_cmpheq: in analyzeCompare()
1558 case Hexagon::A4_cmphgt: in analyzeCompare()
1559 case Hexagon::A4_cmphgtu: in analyzeCompare()
1560 case Hexagon::A4_cmpheqi: in analyzeCompare()
1561 case Hexagon::A4_cmphgti: in analyzeCompare()
1562 case Hexagon::A4_cmphgtui: in analyzeCompare()
1570 case Hexagon::C2_cmpeq: in analyzeCompare()
1571 case Hexagon::C2_cmpeqp: in analyzeCompare()
1572 case Hexagon::C2_cmpgt: in analyzeCompare()
1573 case Hexagon::C2_cmpgtp: in analyzeCompare()
1574 case Hexagon::C2_cmpgtu: in analyzeCompare()
1575 case Hexagon::C2_cmpgtup: in analyzeCompare()
1576 case Hexagon::A4_cmpbeq: in analyzeCompare()
1577 case Hexagon::A4_cmpbgt: in analyzeCompare()
1578 case Hexagon::A4_cmpbgtu: in analyzeCompare()
1579 case Hexagon::A4_cmpheq: in analyzeCompare()
1580 case Hexagon::A4_cmphgt: in analyzeCompare()
1581 case Hexagon::A4_cmphgtu: in analyzeCompare()
1582 case Hexagon::C4_cmpneq: in analyzeCompare()
1583 case Hexagon::C4_cmplte: in analyzeCompare()
1584 case Hexagon::C4_cmplteu: in analyzeCompare()
1588 case Hexagon::C2_cmpeqi: in analyzeCompare()
1589 case Hexagon::C2_cmpgtui: in analyzeCompare()
1590 case Hexagon::C2_cmpgti: in analyzeCompare()
1591 case Hexagon::C4_cmpneqi: in analyzeCompare()
1592 case Hexagon::C4_cmplteui: in analyzeCompare()
1593 case Hexagon::C4_cmpltei: in analyzeCompare()
1594 case Hexagon::A4_cmpbeqi: in analyzeCompare()
1595 case Hexagon::A4_cmpbgti: in analyzeCompare()
1596 case Hexagon::A4_cmpbgtui: in analyzeCompare()
1597 case Hexagon::A4_cmpheqi: in analyzeCompare()
1598 case Hexagon::A4_cmphgti: in analyzeCompare()
1599 case Hexagon::A4_cmphgtui: in analyzeCompare()
1674 if (MI->getOpcode() == Hexagon::A2_addi) { in getIncrementValue()
1687 TRC = &Hexagon::PredRegsRegClass; in createVR()
1689 TRC = &Hexagon::IntRegsRegClass; in createVR()
1691 TRC = &Hexagon::DoubleRegsRegClass; in createVR()
1721 && (MI->getDesc().getOpcode() != Hexagon::S2_allocframe) in isComplex()
1722 && (MI->getDesc().getOpcode() != Hexagon::L2_deallocframe) in isComplex()
1752 case Hexagon::A2_paddf: in isConditionalALU32()
1753 case Hexagon::A2_paddfnew: in isConditionalALU32()
1754 case Hexagon::A2_paddif: in isConditionalALU32()
1755 case Hexagon::A2_paddifnew: in isConditionalALU32()
1756 case Hexagon::A2_paddit: in isConditionalALU32()
1757 case Hexagon::A2_padditnew: in isConditionalALU32()
1758 case Hexagon::A2_paddt: in isConditionalALU32()
1759 case Hexagon::A2_paddtnew: in isConditionalALU32()
1760 case Hexagon::A2_pandf: in isConditionalALU32()
1761 case Hexagon::A2_pandfnew: in isConditionalALU32()
1762 case Hexagon::A2_pandt: in isConditionalALU32()
1763 case Hexagon::A2_pandtnew: in isConditionalALU32()
1764 case Hexagon::A2_porf: in isConditionalALU32()
1765 case Hexagon::A2_porfnew: in isConditionalALU32()
1766 case Hexagon::A2_port: in isConditionalALU32()
1767 case Hexagon::A2_portnew: in isConditionalALU32()
1768 case Hexagon::A2_psubf: in isConditionalALU32()
1769 case Hexagon::A2_psubfnew: in isConditionalALU32()
1770 case Hexagon::A2_psubt: in isConditionalALU32()
1771 case Hexagon::A2_psubtnew: in isConditionalALU32()
1772 case Hexagon::A2_pxorf: in isConditionalALU32()
1773 case Hexagon::A2_pxorfnew: in isConditionalALU32()
1774 case Hexagon::A2_pxort: in isConditionalALU32()
1775 case Hexagon::A2_pxortnew: in isConditionalALU32()
1776 case Hexagon::A4_paslhf: in isConditionalALU32()
1777 case Hexagon::A4_paslhfnew: in isConditionalALU32()
1778 case Hexagon::A4_paslht: in isConditionalALU32()
1779 case Hexagon::A4_paslhtnew: in isConditionalALU32()
1780 case Hexagon::A4_pasrhf: in isConditionalALU32()
1781 case Hexagon::A4_pasrhfnew: in isConditionalALU32()
1782 case Hexagon::A4_pasrht: in isConditionalALU32()
1783 case Hexagon::A4_pasrhtnew: in isConditionalALU32()
1784 case Hexagon::A4_psxtbf: in isConditionalALU32()
1785 case Hexagon::A4_psxtbfnew: in isConditionalALU32()
1786 case Hexagon::A4_psxtbt: in isConditionalALU32()
1787 case Hexagon::A4_psxtbtnew: in isConditionalALU32()
1788 case Hexagon::A4_psxthf: in isConditionalALU32()
1789 case Hexagon::A4_psxthfnew: in isConditionalALU32()
1790 case Hexagon::A4_psxtht: in isConditionalALU32()
1791 case Hexagon::A4_psxthtnew: in isConditionalALU32()
1792 case Hexagon::A4_pzxtbf: in isConditionalALU32()
1793 case Hexagon::A4_pzxtbfnew: in isConditionalALU32()
1794 case Hexagon::A4_pzxtbt: in isConditionalALU32()
1795 case Hexagon::A4_pzxtbtnew: in isConditionalALU32()
1796 case Hexagon::A4_pzxthf: in isConditionalALU32()
1797 case Hexagon::A4_pzxthfnew: in isConditionalALU32()
1798 case Hexagon::A4_pzxtht: in isConditionalALU32()
1799 case Hexagon::A4_pzxthtnew: in isConditionalALU32()
1800 case Hexagon::C2_ccombinewf: in isConditionalALU32()
1801 case Hexagon::C2_ccombinewt: in isConditionalALU32()
1814 int PNewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode()); in isConditionalLoad()
1827 case Hexagon::S4_storeirbt_io: in isConditionalStore()
1828 case Hexagon::S4_storeirbf_io: in isConditionalStore()
1829 case Hexagon::S4_pstorerbt_rr: in isConditionalStore()
1830 case Hexagon::S4_pstorerbf_rr: in isConditionalStore()
1831 case Hexagon::S2_pstorerbt_io: in isConditionalStore()
1832 case Hexagon::S2_pstorerbf_io: in isConditionalStore()
1833 case Hexagon::S2_pstorerbt_pi: in isConditionalStore()
1834 case Hexagon::S2_pstorerbf_pi: in isConditionalStore()
1835 case Hexagon::S2_pstorerdt_io: in isConditionalStore()
1836 case Hexagon::S2_pstorerdf_io: in isConditionalStore()
1837 case Hexagon::S4_pstorerdt_rr: in isConditionalStore()
1838 case Hexagon::S4_pstorerdf_rr: in isConditionalStore()
1839 case Hexagon::S2_pstorerdt_pi: in isConditionalStore()
1840 case Hexagon::S2_pstorerdf_pi: in isConditionalStore()
1841 case Hexagon::S2_pstorerht_io: in isConditionalStore()
1842 case Hexagon::S2_pstorerhf_io: in isConditionalStore()
1843 case Hexagon::S4_storeirht_io: in isConditionalStore()
1844 case Hexagon::S4_storeirhf_io: in isConditionalStore()
1845 case Hexagon::S4_pstorerht_rr: in isConditionalStore()
1846 case Hexagon::S4_pstorerhf_rr: in isConditionalStore()
1847 case Hexagon::S2_pstorerht_pi: in isConditionalStore()
1848 case Hexagon::S2_pstorerhf_pi: in isConditionalStore()
1849 case Hexagon::S2_pstorerit_io: in isConditionalStore()
1850 case Hexagon::S2_pstorerif_io: in isConditionalStore()
1851 case Hexagon::S4_storeirit_io: in isConditionalStore()
1852 case Hexagon::S4_storeirif_io: in isConditionalStore()
1853 case Hexagon::S4_pstorerit_rr: in isConditionalStore()
1854 case Hexagon::S4_pstorerif_rr: in isConditionalStore()
1855 case Hexagon::S2_pstorerit_pi: in isConditionalStore()
1856 case Hexagon::S2_pstorerif_pi: in isConditionalStore()
1859 case Hexagon::S4_pstorerdt_abs: in isConditionalStore()
1860 case Hexagon::S4_pstorerdf_abs: in isConditionalStore()
1861 case Hexagon::S4_pstorerbt_abs: in isConditionalStore()
1862 case Hexagon::S4_pstorerbf_abs: in isConditionalStore()
1863 case Hexagon::S4_pstorerht_abs: in isConditionalStore()
1864 case Hexagon::S4_pstorerhf_abs: in isConditionalStore()
1865 case Hexagon::S4_pstorerit_abs: in isConditionalStore()
1866 case Hexagon::S4_pstorerif_abs: in isConditionalStore()
1880 case Hexagon::A2_tfrt: in isConditionalTransfer()
1881 case Hexagon::A2_tfrf: in isConditionalTransfer()
1882 case Hexagon::C2_cmoveit: in isConditionalTransfer()
1883 case Hexagon::C2_cmoveif: in isConditionalTransfer()
1884 case Hexagon::A2_tfrtnew: in isConditionalTransfer()
1885 case Hexagon::A2_tfrfnew: in isConditionalTransfer()
1886 case Hexagon::C2_cmovenewit: in isConditionalTransfer()
1887 case Hexagon::C2_cmovenewif: in isConditionalTransfer()
1888 case Hexagon::A2_tfrpt: in isConditionalTransfer()
1889 case Hexagon::A2_tfrpf: in isConditionalTransfer()
1950 case Hexagon::L4_return : in isDeallocRet()
1951 case Hexagon::L4_return_t : in isDeallocRet()
1952 case Hexagon::L4_return_f : in isDeallocRet()
1953 case Hexagon::L4_return_tnew_pnt : in isDeallocRet()
1954 case Hexagon::L4_return_fnew_pnt : in isDeallocRet()
1955 case Hexagon::L4_return_tnew_pt : in isDeallocRet()
1956 case Hexagon::L4_return_fnew_pt : in isDeallocRet()
1986 if (Hexagon::DoubleRegsRegClass.contains(RegA)) in isDependent()
1991 if (Hexagon::DoubleRegsRegClass.contains(RegB)) in isDependent()
2004 case Hexagon::V6_vL32b_cur_pi: in isDotCurInst()
2005 case Hexagon::V6_vL32b_cur_ai: in isDotCurInst()
2006 case Hexagon::V6_vL32b_cur_pi_128B: in isDotCurInst()
2007 case Hexagon::V6_vL32b_cur_ai_128B: in isDotCurInst()
2042 if (SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23) in isEarlySourceInstr()
2049 return (Opcode == Hexagon::ENDLOOP0 || in isEndLoopN()
2050 Opcode == Hexagon::ENDLOOP1); in isEndLoopN()
2079 case Hexagon::TFR_FI: in isExtendable()
2127 case Hexagon::J2_callr : in isIndirectCall()
2128 case Hexagon::J2_callrf : in isIndirectCall()
2129 case Hexagon::J2_callrt : in isIndirectCall()
2138 case Hexagon::L4_return : in isIndirectL4Return()
2139 case Hexagon::L4_return_t : in isIndirectL4Return()
2140 case Hexagon::L4_return_f : in isIndirectL4Return()
2141 case Hexagon::L4_return_fnew_pnt : in isIndirectL4Return()
2142 case Hexagon::L4_return_fnew_pt : in isIndirectL4Return()
2143 case Hexagon::L4_return_tnew_pnt : in isIndirectL4Return()
2144 case Hexagon::L4_return_tnew_pt : in isIndirectL4Return()
2153 case Hexagon::J2_jumpr : in isJumpR()
2154 case Hexagon::J2_jumprt : in isJumpR()
2155 case Hexagon::J2_jumprf : in isJumpR()
2156 case Hexagon::J2_jumprtnewpt : in isJumpR()
2157 case Hexagon::J2_jumprfnewpt : in isJumpR()
2158 case Hexagon::J2_jumprtnew : in isJumpR()
2159 case Hexagon::J2_jumprfnew : in isJumpR()
2181 case Hexagon::J2_jump: // bits<24> dst; // r22:2 in isJumpWithinBranchRange()
2182 case Hexagon::J2_call: in isJumpWithinBranchRange()
2183 case Hexagon::CALLv3nr: in isJumpWithinBranchRange()
2185 case Hexagon::J2_jumpt: //bits<17> dst; // r15:2 in isJumpWithinBranchRange()
2186 case Hexagon::J2_jumpf: in isJumpWithinBranchRange()
2187 case Hexagon::J2_jumptnew: in isJumpWithinBranchRange()
2188 case Hexagon::J2_jumptnewpt: in isJumpWithinBranchRange()
2189 case Hexagon::J2_jumpfnew: in isJumpWithinBranchRange()
2190 case Hexagon::J2_jumpfnewpt: in isJumpWithinBranchRange()
2191 case Hexagon::J2_callt: in isJumpWithinBranchRange()
2192 case Hexagon::J2_callf: in isJumpWithinBranchRange()
2194 case Hexagon::J2_loop0i: in isJumpWithinBranchRange()
2195 case Hexagon::J2_loop0iext: in isJumpWithinBranchRange()
2196 case Hexagon::J2_loop0r: in isJumpWithinBranchRange()
2197 case Hexagon::J2_loop0rext: in isJumpWithinBranchRange()
2198 case Hexagon::J2_loop1i: in isJumpWithinBranchRange()
2199 case Hexagon::J2_loop1iext: in isJumpWithinBranchRange()
2200 case Hexagon::J2_loop1r: in isJumpWithinBranchRange()
2201 case Hexagon::J2_loop1rext: in isJumpWithinBranchRange()
2204 case Hexagon::J4_cmpeqi_tp0_jump_nt: in isJumpWithinBranchRange()
2205 case Hexagon::J4_cmpeqi_tp1_jump_nt: in isJumpWithinBranchRange()
2254 case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123: in isLateResultInstr()
2255 case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123: in isLateResultInstr()
2256 case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123: in isLateResultInstr()
2257 case Hexagon::Sched::ALU64_tc_1_SLOT23: in isLateResultInstr()
2258 case Hexagon::Sched::EXTENDER_tc_1_SLOT0123: in isLateResultInstr()
2259 case Hexagon::Sched::S_2op_tc_1_SLOT23: in isLateResultInstr()
2260 case Hexagon::Sched::S_3op_tc_1_SLOT23: in isLateResultInstr()
2261 case Hexagon::Sched::V2LDST_tc_ld_SLOT01: in isLateResultInstr()
2262 case Hexagon::Sched::V2LDST_tc_st_SLOT0: in isLateResultInstr()
2263 case Hexagon::Sched::V2LDST_tc_st_SLOT01: in isLateResultInstr()
2264 case Hexagon::Sched::V4LDST_tc_ld_SLOT01: in isLateResultInstr()
2265 case Hexagon::Sched::V4LDST_tc_st_SLOT0: in isLateResultInstr()
2266 case Hexagon::Sched::V4LDST_tc_st_SLOT01: in isLateResultInstr()
2279 return MI->getDesc().getSchedClass() == Hexagon::Sched::CVI_VX_LATE; in isLateSourceInstr()
2285 return Opcode == Hexagon::J2_loop0i || in isLoopN()
2286 Opcode == Hexagon::J2_loop0r || in isLoopN()
2287 Opcode == Hexagon::J2_loop0iext || in isLoopN()
2288 Opcode == Hexagon::J2_loop0rext || in isLoopN()
2289 Opcode == Hexagon::J2_loop1i || in isLoopN()
2290 Opcode == Hexagon::J2_loop1r || in isLoopN()
2291 Opcode == Hexagon::J2_loop1iext || in isLoopN()
2292 Opcode == Hexagon::J2_loop1rext; in isLoopN()
2299 case Hexagon::L4_iadd_memopw_io : in isMemOp()
2300 case Hexagon::L4_isub_memopw_io : in isMemOp()
2301 case Hexagon::L4_add_memopw_io : in isMemOp()
2302 case Hexagon::L4_sub_memopw_io : in isMemOp()
2303 case Hexagon::L4_and_memopw_io : in isMemOp()
2304 case Hexagon::L4_or_memopw_io : in isMemOp()
2305 case Hexagon::L4_iadd_memoph_io : in isMemOp()
2306 case Hexagon::L4_isub_memoph_io : in isMemOp()
2307 case Hexagon::L4_add_memoph_io : in isMemOp()
2308 case Hexagon::L4_sub_memoph_io : in isMemOp()
2309 case Hexagon::L4_and_memoph_io : in isMemOp()
2310 case Hexagon::L4_or_memoph_io : in isMemOp()
2311 case Hexagon::L4_iadd_memopb_io : in isMemOp()
2312 case Hexagon::L4_isub_memopb_io : in isMemOp()
2313 case Hexagon::L4_add_memopb_io : in isMemOp()
2314 case Hexagon::L4_sub_memopb_io : in isMemOp()
2315 case Hexagon::L4_and_memopb_io : in isMemOp()
2316 case Hexagon::L4_or_memopb_io : in isMemOp()
2317 case Hexagon::L4_ior_memopb_io: in isMemOp()
2318 case Hexagon::L4_ior_memoph_io: in isMemOp()
2319 case Hexagon::L4_ior_memopw_io: in isMemOp()
2320 case Hexagon::L4_iand_memopb_io: in isMemOp()
2321 case Hexagon::L4_iand_memoph_io: in isMemOp()
2322 case Hexagon::L4_iand_memopw_io: in isMemOp()
2433 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 || in isSaveCalleeSavedRegsCall()
2434 MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT || in isSaveCalleeSavedRegsCall()
2435 MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC || in isSaveCalleeSavedRegsCall()
2436 MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC; in isSaveCalleeSavedRegsCall()
2442 case Hexagon::L2_loadrb_io: in isSignExtendingLoad()
2443 case Hexagon::L4_loadrb_ur: in isSignExtendingLoad()
2444 case Hexagon::L4_loadrb_ap: in isSignExtendingLoad()
2445 case Hexagon::L2_loadrb_pr: in isSignExtendingLoad()
2446 case Hexagon::L2_loadrb_pbr: in isSignExtendingLoad()
2447 case Hexagon::L2_loadrb_pi: in isSignExtendingLoad()
2448 case Hexagon::L2_loadrb_pci: in isSignExtendingLoad()
2449 case Hexagon::L2_loadrb_pcr: in isSignExtendingLoad()
2450 case Hexagon::L2_loadbsw2_io: in isSignExtendingLoad()
2451 case Hexagon::L4_loadbsw2_ur: in isSignExtendingLoad()
2452 case Hexagon::L4_loadbsw2_ap: in isSignExtendingLoad()
2453 case Hexagon::L2_loadbsw2_pr: in isSignExtendingLoad()
2454 case Hexagon::L2_loadbsw2_pbr: in isSignExtendingLoad()
2455 case Hexagon::L2_loadbsw2_pi: in isSignExtendingLoad()
2456 case Hexagon::L2_loadbsw2_pci: in isSignExtendingLoad()
2457 case Hexagon::L2_loadbsw2_pcr: in isSignExtendingLoad()
2458 case Hexagon::L2_loadbsw4_io: in isSignExtendingLoad()
2459 case Hexagon::L4_loadbsw4_ur: in isSignExtendingLoad()
2460 case Hexagon::L4_loadbsw4_ap: in isSignExtendingLoad()
2461 case Hexagon::L2_loadbsw4_pr: in isSignExtendingLoad()
2462 case Hexagon::L2_loadbsw4_pbr: in isSignExtendingLoad()
2463 case Hexagon::L2_loadbsw4_pi: in isSignExtendingLoad()
2464 case Hexagon::L2_loadbsw4_pci: in isSignExtendingLoad()
2465 case Hexagon::L2_loadbsw4_pcr: in isSignExtendingLoad()
2466 case Hexagon::L4_loadrb_rr: in isSignExtendingLoad()
2467 case Hexagon::L2_ploadrbt_io: in isSignExtendingLoad()
2468 case Hexagon::L2_ploadrbt_pi: in isSignExtendingLoad()
2469 case Hexagon::L2_ploadrbf_io: in isSignExtendingLoad()
2470 case Hexagon::L2_ploadrbf_pi: in isSignExtendingLoad()
2471 case Hexagon::L2_ploadrbtnew_io: in isSignExtendingLoad()
2472 case Hexagon::L2_ploadrbfnew_io: in isSignExtendingLoad()
2473 case Hexagon::L4_ploadrbt_rr: in isSignExtendingLoad()
2474 case Hexagon::L4_ploadrbf_rr: in isSignExtendingLoad()
2475 case Hexagon::L4_ploadrbtnew_rr: in isSignExtendingLoad()
2476 case Hexagon::L4_ploadrbfnew_rr: in isSignExtendingLoad()
2477 case Hexagon::L2_ploadrbtnew_pi: in isSignExtendingLoad()
2478 case Hexagon::L2_ploadrbfnew_pi: in isSignExtendingLoad()
2479 case Hexagon::L4_ploadrbt_abs: in isSignExtendingLoad()
2480 case Hexagon::L4_ploadrbf_abs: in isSignExtendingLoad()
2481 case Hexagon::L4_ploadrbtnew_abs: in isSignExtendingLoad()
2482 case Hexagon::L4_ploadrbfnew_abs: in isSignExtendingLoad()
2483 case Hexagon::L2_loadrbgp: in isSignExtendingLoad()
2485 case Hexagon::L2_loadrh_io: in isSignExtendingLoad()
2486 case Hexagon::L4_loadrh_ur: in isSignExtendingLoad()
2487 case Hexagon::L4_loadrh_ap: in isSignExtendingLoad()
2488 case Hexagon::L2_loadrh_pr: in isSignExtendingLoad()
2489 case Hexagon::L2_loadrh_pbr: in isSignExtendingLoad()
2490 case Hexagon::L2_loadrh_pi: in isSignExtendingLoad()
2491 case Hexagon::L2_loadrh_pci: in isSignExtendingLoad()
2492 case Hexagon::L2_loadrh_pcr: in isSignExtendingLoad()
2493 case Hexagon::L4_loadrh_rr: in isSignExtendingLoad()
2494 case Hexagon::L2_ploadrht_io: in isSignExtendingLoad()
2495 case Hexagon::L2_ploadrht_pi: in isSignExtendingLoad()
2496 case Hexagon::L2_ploadrhf_io: in isSignExtendingLoad()
2497 case Hexagon::L2_ploadrhf_pi: in isSignExtendingLoad()
2498 case Hexagon::L2_ploadrhtnew_io: in isSignExtendingLoad()
2499 case Hexagon::L2_ploadrhfnew_io: in isSignExtendingLoad()
2500 case Hexagon::L4_ploadrht_rr: in isSignExtendingLoad()
2501 case Hexagon::L4_ploadrhf_rr: in isSignExtendingLoad()
2502 case Hexagon::L4_ploadrhtnew_rr: in isSignExtendingLoad()
2503 case Hexagon::L4_ploadrhfnew_rr: in isSignExtendingLoad()
2504 case Hexagon::L2_ploadrhtnew_pi: in isSignExtendingLoad()
2505 case Hexagon::L2_ploadrhfnew_pi: in isSignExtendingLoad()
2506 case Hexagon::L4_ploadrht_abs: in isSignExtendingLoad()
2507 case Hexagon::L4_ploadrhf_abs: in isSignExtendingLoad()
2508 case Hexagon::L4_ploadrhtnew_abs: in isSignExtendingLoad()
2509 case Hexagon::L4_ploadrhfnew_abs: in isSignExtendingLoad()
2510 case Hexagon::L2_loadrhgp: in isSignExtendingLoad()
2526 case Hexagon::STriw_pred : in isSpillPredRegOp()
2527 case Hexagon::LDriw_pred : in isSpillPredRegOp()
2550 case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123: in isTC1()
2551 case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123: in isTC1()
2552 case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123: in isTC1()
2553 case Hexagon::Sched::ALU64_tc_1_SLOT23: in isTC1()
2554 case Hexagon::Sched::EXTENDER_tc_1_SLOT0123: in isTC1()
2556 case Hexagon::Sched::S_2op_tc_1_SLOT23: in isTC1()
2557 case Hexagon::Sched::S_3op_tc_1_SLOT23: in isTC1()
2569 case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123: in isTC2()
2570 case Hexagon::Sched::ALU64_tc_2_SLOT23: in isTC2()
2571 case Hexagon::Sched::CR_tc_2_SLOT3: in isTC2()
2572 case Hexagon::Sched::M_tc_2_SLOT23: in isTC2()
2573 case Hexagon::Sched::S_2op_tc_2_SLOT23: in isTC2()
2574 case Hexagon::Sched::S_3op_tc_2_SLOT23: in isTC2()
2586 case Hexagon::Sched::ALU32_2op_tc_2early_SLOT0123: in isTC2Early()
2587 case Hexagon::Sched::ALU32_3op_tc_2early_SLOT0123: in isTC2Early()
2588 case Hexagon::Sched::ALU64_tc_2early_SLOT23: in isTC2Early()
2589 case Hexagon::Sched::CR_tc_2early_SLOT23: in isTC2Early()
2590 case Hexagon::Sched::CR_tc_2early_SLOT3: in isTC2Early()
2591 case Hexagon::Sched::J_tc_2early_SLOT0123: in isTC2Early()
2592 case Hexagon::Sched::J_tc_2early_SLOT2: in isTC2Early()
2593 case Hexagon::Sched::J_tc_2early_SLOT23: in isTC2Early()
2594 case Hexagon::Sched::S_2op_tc_2early_SLOT23: in isTC2Early()
2595 case Hexagon::Sched::S_3op_tc_2early_SLOT23: in isTC2Early()
2609 return SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23; in isTC4x()
2673 case Hexagon::STriq_pred_V6: in isValidOffset()
2674 case Hexagon::STriq_pred_vec_V6: in isValidOffset()
2675 case Hexagon::STriv_pseudo_V6: in isValidOffset()
2676 case Hexagon::STrivv_pseudo_V6: in isValidOffset()
2677 case Hexagon::LDriq_pred_V6: in isValidOffset()
2678 case Hexagon::LDriq_pred_vec_V6: in isValidOffset()
2679 case Hexagon::LDriv_pseudo_V6: in isValidOffset()
2680 case Hexagon::LDrivv_pseudo_V6: in isValidOffset()
2681 case Hexagon::LDrivv_indexed: in isValidOffset()
2682 case Hexagon::STrivv_indexed: in isValidOffset()
2683 case Hexagon::V6_vL32b_ai: in isValidOffset()
2684 case Hexagon::V6_vS32b_ai: in isValidOffset()
2685 case Hexagon::V6_vL32Ub_ai: in isValidOffset()
2686 case Hexagon::V6_vS32Ub_ai: in isValidOffset()
2690 case Hexagon::STriq_pred_V6_128B: in isValidOffset()
2691 case Hexagon::STriq_pred_vec_V6_128B: in isValidOffset()
2692 case Hexagon::STriv_pseudo_V6_128B: in isValidOffset()
2693 case Hexagon::STrivv_pseudo_V6_128B: in isValidOffset()
2694 case Hexagon::LDriq_pred_V6_128B: in isValidOffset()
2695 case Hexagon::LDriq_pred_vec_V6_128B: in isValidOffset()
2696 case Hexagon::LDriv_pseudo_V6_128B: in isValidOffset()
2697 case Hexagon::LDrivv_pseudo_V6_128B: in isValidOffset()
2698 case Hexagon::LDrivv_indexed_128B: in isValidOffset()
2699 case Hexagon::STrivv_indexed_128B: in isValidOffset()
2700 case Hexagon::V6_vL32b_ai_128B: in isValidOffset()
2701 case Hexagon::V6_vS32b_ai_128B: in isValidOffset()
2702 case Hexagon::V6_vL32Ub_ai_128B: in isValidOffset()
2703 case Hexagon::V6_vS32Ub_ai_128B: in isValidOffset()
2707 case Hexagon::J2_loop0i: in isValidOffset()
2708 case Hexagon::J2_loop1i: in isValidOffset()
2716 case Hexagon::L2_loadri_io: in isValidOffset()
2717 case Hexagon::S2_storeri_io: in isValidOffset()
2721 case Hexagon::L2_loadrd_io: in isValidOffset()
2722 case Hexagon::S2_storerd_io: in isValidOffset()
2726 case Hexagon::L2_loadrh_io: in isValidOffset()
2727 case Hexagon::L2_loadruh_io: in isValidOffset()
2728 case Hexagon::S2_storerh_io: in isValidOffset()
2732 case Hexagon::L2_loadrb_io: in isValidOffset()
2733 case Hexagon::L2_loadrub_io: in isValidOffset()
2734 case Hexagon::S2_storerb_io: in isValidOffset()
2738 case Hexagon::A2_addi: in isValidOffset()
2742 case Hexagon::L4_iadd_memopw_io : in isValidOffset()
2743 case Hexagon::L4_isub_memopw_io : in isValidOffset()
2744 case Hexagon::L4_add_memopw_io : in isValidOffset()
2745 case Hexagon::L4_sub_memopw_io : in isValidOffset()
2746 case Hexagon::L4_and_memopw_io : in isValidOffset()
2747 case Hexagon::L4_or_memopw_io : in isValidOffset()
2750 case Hexagon::L4_iadd_memoph_io : in isValidOffset()
2751 case Hexagon::L4_isub_memoph_io : in isValidOffset()
2752 case Hexagon::L4_add_memoph_io : in isValidOffset()
2753 case Hexagon::L4_sub_memoph_io : in isValidOffset()
2754 case Hexagon::L4_and_memoph_io : in isValidOffset()
2755 case Hexagon::L4_or_memoph_io : in isValidOffset()
2758 case Hexagon::L4_iadd_memopb_io : in isValidOffset()
2759 case Hexagon::L4_isub_memopb_io : in isValidOffset()
2760 case Hexagon::L4_add_memopb_io : in isValidOffset()
2761 case Hexagon::L4_sub_memopb_io : in isValidOffset()
2762 case Hexagon::L4_and_memopb_io : in isValidOffset()
2763 case Hexagon::L4_or_memopb_io : in isValidOffset()
2768 case Hexagon::STriw_pred: in isValidOffset()
2769 case Hexagon::LDriw_pred: in isValidOffset()
2770 case Hexagon::STriw_mod: in isValidOffset()
2771 case Hexagon::LDriw_mod: in isValidOffset()
2774 case Hexagon::TFR_FI: in isValidOffset()
2775 case Hexagon::TFR_FIA: in isValidOffset()
2776 case Hexagon::INLINEASM: in isValidOffset()
2779 case Hexagon::L2_ploadrbt_io: in isValidOffset()
2780 case Hexagon::L2_ploadrbf_io: in isValidOffset()
2781 case Hexagon::L2_ploadrubt_io: in isValidOffset()
2782 case Hexagon::L2_ploadrubf_io: in isValidOffset()
2783 case Hexagon::S2_pstorerbt_io: in isValidOffset()
2784 case Hexagon::S2_pstorerbf_io: in isValidOffset()
2785 case Hexagon::S4_storeirb_io: in isValidOffset()
2786 case Hexagon::S4_storeirbt_io: in isValidOffset()
2787 case Hexagon::S4_storeirbf_io: in isValidOffset()
2790 case Hexagon::L2_ploadrht_io: in isValidOffset()
2791 case Hexagon::L2_ploadrhf_io: in isValidOffset()
2792 case Hexagon::L2_ploadruht_io: in isValidOffset()
2793 case Hexagon::L2_ploadruhf_io: in isValidOffset()
2794 case Hexagon::S2_pstorerht_io: in isValidOffset()
2795 case Hexagon::S2_pstorerhf_io: in isValidOffset()
2796 case Hexagon::S4_storeirh_io: in isValidOffset()
2797 case Hexagon::S4_storeirht_io: in isValidOffset()
2798 case Hexagon::S4_storeirhf_io: in isValidOffset()
2801 case Hexagon::L2_ploadrit_io: in isValidOffset()
2802 case Hexagon::L2_ploadrif_io: in isValidOffset()
2803 case Hexagon::S2_pstorerit_io: in isValidOffset()
2804 case Hexagon::S2_pstorerif_io: in isValidOffset()
2805 case Hexagon::S4_storeiri_io: in isValidOffset()
2806 case Hexagon::S4_storeirit_io: in isValidOffset()
2807 case Hexagon::S4_storeirif_io: in isValidOffset()
2810 case Hexagon::L2_ploadrdt_io: in isValidOffset()
2811 case Hexagon::L2_ploadrdf_io: in isValidOffset()
2812 case Hexagon::S2_pstorerdt_io: in isValidOffset()
2813 case Hexagon::S2_pstorerdf_io: in isValidOffset()
2855 case Hexagon::L2_loadrub_io: in isZeroExtendingLoad()
2856 case Hexagon::L4_loadrub_ur: in isZeroExtendingLoad()
2857 case Hexagon::L4_loadrub_ap: in isZeroExtendingLoad()
2858 case Hexagon::L2_loadrub_pr: in isZeroExtendingLoad()
2859 case Hexagon::L2_loadrub_pbr: in isZeroExtendingLoad()
2860 case Hexagon::L2_loadrub_pi: in isZeroExtendingLoad()
2861 case Hexagon::L2_loadrub_pci: in isZeroExtendingLoad()
2862 case Hexagon::L2_loadrub_pcr: in isZeroExtendingLoad()
2863 case Hexagon::L2_loadbzw2_io: in isZeroExtendingLoad()
2864 case Hexagon::L4_loadbzw2_ur: in isZeroExtendingLoad()
2865 case Hexagon::L4_loadbzw2_ap: in isZeroExtendingLoad()
2866 case Hexagon::L2_loadbzw2_pr: in isZeroExtendingLoad()
2867 case Hexagon::L2_loadbzw2_pbr: in isZeroExtendingLoad()
2868 case Hexagon::L2_loadbzw2_pi: in isZeroExtendingLoad()
2869 case Hexagon::L2_loadbzw2_pci: in isZeroExtendingLoad()
2870 case Hexagon::L2_loadbzw2_pcr: in isZeroExtendingLoad()
2871 case Hexagon::L2_loadbzw4_io: in isZeroExtendingLoad()
2872 case Hexagon::L4_loadbzw4_ur: in isZeroExtendingLoad()
2873 case Hexagon::L4_loadbzw4_ap: in isZeroExtendingLoad()
2874 case Hexagon::L2_loadbzw4_pr: in isZeroExtendingLoad()
2875 case Hexagon::L2_loadbzw4_pbr: in isZeroExtendingLoad()
2876 case Hexagon::L2_loadbzw4_pi: in isZeroExtendingLoad()
2877 case Hexagon::L2_loadbzw4_pci: in isZeroExtendingLoad()
2878 case Hexagon::L2_loadbzw4_pcr: in isZeroExtendingLoad()
2879 case Hexagon::L4_loadrub_rr: in isZeroExtendingLoad()
2880 case Hexagon::L2_ploadrubt_io: in isZeroExtendingLoad()
2881 case Hexagon::L2_ploadrubt_pi: in isZeroExtendingLoad()
2882 case Hexagon::L2_ploadrubf_io: in isZeroExtendingLoad()
2883 case Hexagon::L2_ploadrubf_pi: in isZeroExtendingLoad()
2884 case Hexagon::L2_ploadrubtnew_io: in isZeroExtendingLoad()
2885 case Hexagon::L2_ploadrubfnew_io: in isZeroExtendingLoad()
2886 case Hexagon::L4_ploadrubt_rr: in isZeroExtendingLoad()
2887 case Hexagon::L4_ploadrubf_rr: in isZeroExtendingLoad()
2888 case Hexagon::L4_ploadrubtnew_rr: in isZeroExtendingLoad()
2889 case Hexagon::L4_ploadrubfnew_rr: in isZeroExtendingLoad()
2890 case Hexagon::L2_ploadrubtnew_pi: in isZeroExtendingLoad()
2891 case Hexagon::L2_ploadrubfnew_pi: in isZeroExtendingLoad()
2892 case Hexagon::L4_ploadrubt_abs: in isZeroExtendingLoad()
2893 case Hexagon::L4_ploadrubf_abs: in isZeroExtendingLoad()
2894 case Hexagon::L4_ploadrubtnew_abs: in isZeroExtendingLoad()
2895 case Hexagon::L4_ploadrubfnew_abs: in isZeroExtendingLoad()
2896 case Hexagon::L2_loadrubgp: in isZeroExtendingLoad()
2898 case Hexagon::L2_loadruh_io: in isZeroExtendingLoad()
2899 case Hexagon::L4_loadruh_ur: in isZeroExtendingLoad()
2900 case Hexagon::L4_loadruh_ap: in isZeroExtendingLoad()
2901 case Hexagon::L2_loadruh_pr: in isZeroExtendingLoad()
2902 case Hexagon::L2_loadruh_pbr: in isZeroExtendingLoad()
2903 case Hexagon::L2_loadruh_pi: in isZeroExtendingLoad()
2904 case Hexagon::L2_loadruh_pci: in isZeroExtendingLoad()
2905 case Hexagon::L2_loadruh_pcr: in isZeroExtendingLoad()
2906 case Hexagon::L4_loadruh_rr: in isZeroExtendingLoad()
2907 case Hexagon::L2_ploadruht_io: in isZeroExtendingLoad()
2908 case Hexagon::L2_ploadruht_pi: in isZeroExtendingLoad()
2909 case Hexagon::L2_ploadruhf_io: in isZeroExtendingLoad()
2910 case Hexagon::L2_ploadruhf_pi: in isZeroExtendingLoad()
2911 case Hexagon::L2_ploadruhtnew_io: in isZeroExtendingLoad()
2912 case Hexagon::L2_ploadruhfnew_io: in isZeroExtendingLoad()
2913 case Hexagon::L4_ploadruht_rr: in isZeroExtendingLoad()
2914 case Hexagon::L4_ploadruhf_rr: in isZeroExtendingLoad()
2915 case Hexagon::L4_ploadruhtnew_rr: in isZeroExtendingLoad()
2916 case Hexagon::L4_ploadruhfnew_rr: in isZeroExtendingLoad()
2917 case Hexagon::L2_ploadruhtnew_pi: in isZeroExtendingLoad()
2918 case Hexagon::L2_ploadruhfnew_pi: in isZeroExtendingLoad()
2919 case Hexagon::L4_ploadruht_abs: in isZeroExtendingLoad()
2920 case Hexagon::L4_ploadruhf_abs: in isZeroExtendingLoad()
2921 case Hexagon::L4_ploadruhtnew_abs: in isZeroExtendingLoad()
2922 case Hexagon::L4_ploadruhfnew_abs: in isZeroExtendingLoad()
2923 case Hexagon::L2_loadruhgp: in isZeroExtendingLoad()
2989 if (Hexagon::getRegForm(MI->getOpcode()) >= 0) in hasNonExtEquivalent()
2999 NonExtOpcode = Hexagon::getBaseWithImmOffset(MI->getOpcode()); in hasNonExtEquivalent()
3005 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode()); in hasNonExtEquivalent()
3008 NonExtOpcode = Hexagon::getRegShlForm(MI->getOpcode()); in hasNonExtEquivalent()
3022 return Hexagon::getRealHWInstr(MI->getOpcode(), in hasPseudoInstrPair()
3023 Hexagon::InstrType_Pseudo) >= 0; in hasPseudoInstrPair()
3112 return MI->getOpcode() != Hexagon::A4_tlbmatch; in predCanBeUsedAsDotNew()
3117 return (Opcode == Hexagon::J2_jumpt) || in PredOpcodeHasJMP_c()
3118 (Opcode == Hexagon::J2_jumpf) || in PredOpcodeHasJMP_c()
3119 (Opcode == Hexagon::J2_jumptnew) || in PredOpcodeHasJMP_c()
3120 (Opcode == Hexagon::J2_jumpfnew) || in PredOpcodeHasJMP_c()
3121 (Opcode == Hexagon::J2_jumptnewpt) || in PredOpcodeHasJMP_c()
3122 (Opcode == Hexagon::J2_jumpfnewpt); in PredOpcodeHasJMP_c()
3134 return Hexagon::getAbsoluteForm(MI->getOpcode()); in getAbsoluteForm()
3280 return Hexagon::getBaseWithLongOffset(Opcode); in getBaseWithLongOffset()
3285 return Hexagon::getBaseWithLongOffset(MI->getOpcode()); in getBaseWithLongOffset()
3290 return Hexagon::getBaseWithRegOffset(MI->getOpcode()); in getBaseWithRegOffset()
3315 case Hexagon::C2_cmpeq: in getCompoundCandidateGroup()
3316 case Hexagon::C2_cmpgt: in getCompoundCandidateGroup()
3317 case Hexagon::C2_cmpgtu: in getCompoundCandidateGroup()
3321 if (Hexagon::PredRegsRegClass.contains(DstReg) && in getCompoundCandidateGroup()
3322 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
3326 case Hexagon::C2_cmpeqi: in getCompoundCandidateGroup()
3327 case Hexagon::C2_cmpgti: in getCompoundCandidateGroup()
3328 case Hexagon::C2_cmpgtui: in getCompoundCandidateGroup()
3332 if (Hexagon::PredRegsRegClass.contains(DstReg) && in getCompoundCandidateGroup()
3333 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
3339 case Hexagon::A2_tfr: in getCompoundCandidateGroup()
3346 case Hexagon::A2_tfrsi: in getCompoundCandidateGroup()
3354 case Hexagon::S2_tstbit_i: in getCompoundCandidateGroup()
3357 if (Hexagon::PredRegsRegClass.contains(DstReg) && in getCompoundCandidateGroup()
3358 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
3367 case Hexagon::J2_jumptnew: in getCompoundCandidateGroup()
3368 case Hexagon::J2_jumpfnew: in getCompoundCandidateGroup()
3369 case Hexagon::J2_jumptnewpt: in getCompoundCandidateGroup()
3370 case Hexagon::J2_jumpfnewpt: in getCompoundCandidateGroup()
3372 if (Hexagon::PredRegsRegClass.contains(Src1Reg) && in getCompoundCandidateGroup()
3373 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg)) in getCompoundCandidateGroup()
3380 case Hexagon::J2_jump: in getCompoundCandidateGroup()
3381 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4: in getCompoundCandidateGroup()
3395 if ((GA->getOpcode() != Hexagon::C2_cmpeqi) || in getCompoundOpcode()
3396 (GB->getOpcode() != Hexagon::J2_jumptnew)) in getCompoundOpcode()
3401 if (DestReg == Hexagon::P0) in getCompoundOpcode()
3402 return Hexagon::J4_cmpeqi_tp0_jump_nt; in getCompoundOpcode()
3403 if (DestReg == Hexagon::P1) in getCompoundOpcode()
3404 return Hexagon::J4_cmpeqi_tp1_jump_nt; in getCompoundOpcode()
3410 enum Hexagon::PredSense inPredSense; in getCondOpcode()
3411 inPredSense = invertPredicate ? Hexagon::PredSense_false : in getCondOpcode()
3412 Hexagon::PredSense_true; in getCondOpcode()
3413 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense); in getCondOpcode()
3420 case Hexagon::TFRI_f: in getCondOpcode()
3421 return !invertPredicate ? Hexagon::TFRI_cPt_f : in getCondOpcode()
3422 Hexagon::TFRI_cNotPt_f; in getCondOpcode()
3433 case Hexagon::V6_vL32b_pi: in getDotCurOp()
3434 return Hexagon::V6_vL32b_cur_pi; in getDotCurOp()
3435 case Hexagon::V6_vL32b_ai: in getDotCurOp()
3436 return Hexagon::V6_vL32b_cur_ai; in getDotCurOp()
3438 case Hexagon::V6_vL32b_pi_128B: in getDotCurOp()
3439 return Hexagon::V6_vL32b_cur_pi_128B; in getDotCurOp()
3440 case Hexagon::V6_vL32b_ai_128B: in getDotCurOp()
3441 return Hexagon::V6_vL32b_cur_ai_128B; in getDotCurOp()
3530 int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode()); in getDotNewOp()
3536 case Hexagon::S4_storerb_ur: in getDotNewOp()
3537 return Hexagon::S4_storerbnew_ur; in getDotNewOp()
3539 case Hexagon::S2_storerb_pci: in getDotNewOp()
3540 return Hexagon::S2_storerb_pci; in getDotNewOp()
3542 case Hexagon::S2_storeri_pci: in getDotNewOp()
3543 return Hexagon::S2_storeri_pci; in getDotNewOp()
3545 case Hexagon::S2_storerh_pci: in getDotNewOp()
3546 return Hexagon::S2_storerh_pci; in getDotNewOp()
3548 case Hexagon::S2_storerd_pci: in getDotNewOp()
3549 return Hexagon::S2_storerd_pci; in getDotNewOp()
3551 case Hexagon::S2_storerf_pci: in getDotNewOp()
3552 return Hexagon::S2_storerf_pci; in getDotNewOp()
3554 case Hexagon::V6_vS32b_ai: in getDotNewOp()
3555 return Hexagon::V6_vS32b_new_ai; in getDotNewOp()
3557 case Hexagon::V6_vS32b_pi: in getDotNewOp()
3558 return Hexagon::V6_vS32b_new_pi; in getDotNewOp()
3561 case Hexagon::V6_vS32b_ai_128B: in getDotNewOp()
3562 return Hexagon::V6_vS32b_new_ai_128B; in getDotNewOp()
3564 case Hexagon::V6_vS32b_pi_128B: in getDotNewOp()
3565 return Hexagon::V6_vS32b_new_pi_128B; in getDotNewOp()
3587 case Hexagon::J2_jumpt: in getDotNewPredJumpOp()
3588 return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew; in getDotNewPredJumpOp()
3589 case Hexagon::J2_jumpf: in getDotNewPredJumpOp()
3590 return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew; in getDotNewPredJumpOp()
3601 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode()); in getDotNewPredOp()
3607 case Hexagon::J2_jumpt: in getDotNewPredOp()
3608 case Hexagon::J2_jumpf: in getDotNewPredOp()
3621 NewOp = Hexagon::getPredOldOpcode(NewOp); in getDotOldOp()
3627 NewOp = Hexagon::getNonNVStore(NewOp); in getDotOldOp()
3649 case Hexagon::L2_loadri_io: in getDuplexCandidateGroup()
3655 if (Hexagon::IntRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
3667 case Hexagon::L2_loadrub_io: in getDuplexCandidateGroup()
3685 case Hexagon::L2_loadrh_io: in getDuplexCandidateGroup()
3686 case Hexagon::L2_loadruh_io: in getDuplexCandidateGroup()
3695 case Hexagon::L2_loadrb_io: in getDuplexCandidateGroup()
3704 case Hexagon::L2_loadrd_io: in getDuplexCandidateGroup()
3709 Hexagon::IntRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
3717 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4: in getDuplexCandidateGroup()
3718 case Hexagon::L4_return: in getDuplexCandidateGroup()
3719 case Hexagon::L2_deallocframe: in getDuplexCandidateGroup()
3721 case Hexagon::EH_RETURN_JMPR: in getDuplexCandidateGroup()
3722 case Hexagon::JMPret : in getDuplexCandidateGroup()
3726 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)) in getDuplexCandidateGroup()
3729 case Hexagon::JMPrett: in getDuplexCandidateGroup()
3730 case Hexagon::JMPretf: in getDuplexCandidateGroup()
3731 case Hexagon::JMPrettnewpt: in getDuplexCandidateGroup()
3732 case Hexagon::JMPretfnewpt : in getDuplexCandidateGroup()
3733 case Hexagon::JMPrettnew : in getDuplexCandidateGroup()
3734 case Hexagon::JMPretfnew : in getDuplexCandidateGroup()
3738 if ((Hexagon::PredRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
3739 (Hexagon::P0 == SrcReg)) && in getDuplexCandidateGroup()
3740 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))) in getDuplexCandidateGroup()
3743 case Hexagon::L4_return_t : in getDuplexCandidateGroup()
3744 case Hexagon::L4_return_f : in getDuplexCandidateGroup()
3745 case Hexagon::L4_return_tnew_pnt : in getDuplexCandidateGroup()
3746 case Hexagon::L4_return_fnew_pnt : in getDuplexCandidateGroup()
3747 case Hexagon::L4_return_tnew_pt : in getDuplexCandidateGroup()
3748 case Hexagon::L4_return_fnew_pt : in getDuplexCandidateGroup()
3751 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg)) in getDuplexCandidateGroup()
3759 case Hexagon::S2_storeri_io: in getDuplexCandidateGroup()
3764 if (Hexagon::IntRegsRegClass.contains(Src1Reg) && in getDuplexCandidateGroup()
3775 case Hexagon::S2_storerb_io: in getDuplexCandidateGroup()
3792 case Hexagon::S2_storerh_io: in getDuplexCandidateGroup()
3801 case Hexagon::S2_storerd_io: in getDuplexCandidateGroup()
3806 Hexagon::IntRegsRegClass.contains(Src1Reg) && in getDuplexCandidateGroup()
3811 case Hexagon::S4_storeiri_io: in getDuplexCandidateGroup()
3819 case Hexagon::S4_storeirb_io: in getDuplexCandidateGroup()
3827 case Hexagon::S2_allocframe: in getDuplexCandidateGroup()
3850 case Hexagon::A2_addi: in getDuplexCandidateGroup()
3855 if (Hexagon::IntRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
3871 case Hexagon::A2_add: in getDuplexCandidateGroup()
3880 case Hexagon::A2_andir: in getDuplexCandidateGroup()
3892 case Hexagon::A2_tfr: in getDuplexCandidateGroup()
3899 case Hexagon::A2_tfrsi: in getDuplexCandidateGroup()
3908 case Hexagon::C2_cmoveit: in getDuplexCandidateGroup()
3909 case Hexagon::C2_cmovenewit: in getDuplexCandidateGroup()
3910 case Hexagon::C2_cmoveif: in getDuplexCandidateGroup()
3911 case Hexagon::C2_cmovenewif: in getDuplexCandidateGroup()
3918 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg && in getDuplexCandidateGroup()
3922 case Hexagon::C2_cmpeqi: in getDuplexCandidateGroup()
3926 if (Hexagon::PredRegsRegClass.contains(DstReg) && in getDuplexCandidateGroup()
3927 Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
3931 case Hexagon::A2_combineii: in getDuplexCandidateGroup()
3932 case Hexagon::A4_combineii: in getDuplexCandidateGroup()
3944 case Hexagon::A4_combineri: in getDuplexCandidateGroup()
3953 case Hexagon::A4_combineir: in getDuplexCandidateGroup()
3962 case Hexagon::A2_sxtb: in getDuplexCandidateGroup()
3963 case Hexagon::A2_sxth: in getDuplexCandidateGroup()
3964 case Hexagon::A2_zxtb: in getDuplexCandidateGroup()
3965 case Hexagon::A2_zxth: in getDuplexCandidateGroup()
3979 return Hexagon::getRealHWInstr(MI->getOpcode(), Hexagon::InstrType_Real); in getEquivalentHWInstr()
4033 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc) in getInvertedPredicatedOpcode()
4034 : Hexagon::getTruePredOpcode(Opc); in getInvertedPredicatedOpcode()
4082 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode()); in getNonExtOpcode()
4090 return Hexagon::getBaseWithImmOffset(MI->getOpcode()); in getNonExtOpcode()
4092 return Hexagon::getBaseWithRegOffset(MI->getOpcode()); in getNonExtOpcode()
4094 return Hexagon::getRegShlForm(MI->getOpcode()); in getNonExtOpcode()
4126 return Hexagon::getRealHWInstr(MI->getOpcode(), Hexagon::InstrType_Pseudo); in getPseudoInstrPair()
4131 return Hexagon::getRegForm(MI->getOpcode()); in getRegForm()
4153 if (BranchRelaxAsmLarge && MI->getOpcode() == Hexagon::INLINEASM) { in getSize()
4257 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) { in genAllInsnTimingClasses()
4281 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode); in reversePrediction()
4283 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode); in reversePrediction()
4297 return Hexagon::xformRegToImmOffset(MI->getOpcode()); in xformRegToImmOffset()