Lines Matching refs:SLOT2

21 //    | SLOT2     |  XTYPE          ALU32     J         JR           |
43       ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
46                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
48                       [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
50                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
52                       [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
54                       [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
56                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
59         InstrItinData<ALU64_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>]>,
60         InstrItinData<ALU64_tc_2_SLOT23     , [InstrStage<2, [SLOT2, SLOT3]>]>,
61         InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
62         InstrItinData<ALU64_tc_3x_SLOT23    , [InstrStage<3, [SLOT2, SLOT3]>]>,
70         InstrItinData<CR_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
71         InstrItinData<CR_tc_3x_SLOT23    , [InstrStage<3, [SLOT2, SLOT3]>]>,
72         InstrItinData<CJ_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>]>,
73         InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
74         InstrItinData<J_tc_2early_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
75         InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT     , [InstrStage<1, [SLOT2, SLOT3]>]>,
78         InstrItinData<J_tc_2early_SLOT2  , [InstrStage<2, [SLOT2]>]>,
79         InstrItinData<J_tc_3stall_SLOT2  , [InstrStage<3, [SLOT2]>]>,
83                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
91         InstrItinData<M_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>]>,
92         InstrItinData<M_tc_2_SLOT23     , [InstrStage<2, [SLOT2, SLOT3]>]>,
93         InstrItinData<M_tc_3_SLOT23     , [InstrStage<3, [SLOT2, SLOT3]>]>,
94         InstrItinData<M_tc_3x_SLOT23    , [InstrStage<3, [SLOT2, SLOT3]>]>,
95         InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
96         InstrItinData<M_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
115         InstrItinData<S_2op_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>]>,
116         InstrItinData<S_2op_tc_2_SLOT23     , [InstrStage<2, [SLOT2, SLOT3]>]>,
117         InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
118         InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
119         InstrItinData<S_3op_tc_1_SLOT23     , [InstrStage<1, [SLOT2, SLOT3]>]>,
120         InstrItinData<S_3op_tc_2_SLOT23     , [InstrStage<2, [SLOT2, SLOT3]>]>,
121         InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
122         InstrItinData<S_3op_tc_3_SLOT23     , [InstrStage<3, [SLOT2, SLOT3]>]>,
123         InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
124         InstrItinData<S_3op_tc_3x_SLOT23    , [InstrStage<3, [SLOT2, SLOT3]>]>,
144                       [InstrStage<3, [SLOT2, SLOT3]>]>,
146                       [InstrStage<3, [SLOT2, SLOT3]>]>,
148                       [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
151         InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
152         InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>,
154         InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
155         InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
156         InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
157                                 InstrStage<1, [SLOT2, SLOT3]>]>