Lines Matching refs:IDLoc
134 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
176 MacroExpanderResultTy tryExpandInstruction(MCInst &Inst, SMLoc IDLoc,
180 bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
184 bool Is32BitImm, bool IsAddress, SMLoc IDLoc,
188 unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc,
191 bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
196 SMLoc IDLoc, MCStreamer &Out,
199 bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
202 void expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
205 void expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
208 void expandStoreInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
211 bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
214 bool expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
217 bool expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
220 bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
223 bool expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
227 bool expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc,
230 bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out,
233 bool expandUlw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
236 bool expandRotation(MCInst &Inst, SMLoc IDLoc,
238 bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
240 bool expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
242 bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
245 bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
325 bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
1508 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, in processInstruction() argument
1515 Inst.setLoc(IDLoc); in processInstruction()
1540 return Error(IDLoc, "branch target out of range"); in processInstruction()
1543 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1570 return Error(IDLoc, "branch target out of range"); in processInstruction()
1573 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1584 return Error(IDLoc, "branch target out of range"); in processInstruction()
1586 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1595 Warning(IDLoc, "ssnop is deprecated for " + ISA + " and is equivalent to a " in processInstruction()
1616 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
1620 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
1633 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
1636 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
1645 warnIfNoMacro(IDLoc); in processInstruction()
1652 return Error(IDLoc, "jal doesn't support multiple symbols in PIC mode"); in processInstruction()
1675 MCOperand::createExpr(Got16RelocExpr), IDLoc, STI); in processInstruction()
1677 MCOperand::createExpr(Lo16RelocExpr), IDLoc, STI); in processInstruction()
1688 Mips::GP, MCOperand::createExpr(GotDispRelocExpr), IDLoc, in processInstruction()
1700 MCOperand::createExpr(Call16RelocExpr), IDLoc, STI); in processInstruction()
1731 expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), true); in processInstruction()
1741 expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), false); in processInstruction()
1745 expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), false); in processInstruction()
1772 IDLoc, STI); in processInstruction()
1791 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
1795 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
1801 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
1804 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
1809 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
1812 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
1817 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
1821 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
1826 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
1831 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
1836 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
1839 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
1845 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
1848 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
1855 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
1858 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
1865 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
1868 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
1873 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
1876 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
1887 tryExpandInstruction(Inst, IDLoc, Out, STI); in processInstruction()
1906 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst.getOpcode()), IDLoc, STI); in processInstruction()
1918 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst.getOpcode()), IDLoc, in processInstruction()
1922 TOut.emitGPRestore(CpRestoreOffset, IDLoc, STI); in processInstruction()
1924 Warning(IDLoc, "no .cprestore used in PIC mode"); in processInstruction()
1931 MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in tryExpandInstruction() argument
1937 return expandLoadImm(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
1939 return expandLoadImm(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
1948 Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc, in tryExpandInstruction()
1961 Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc, in tryExpandInstruction()
1967 return expandUncondBranchMMPseudo(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
1971 return expandLoadStoreMultiple(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
1975 return expandJalWithRegs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
1978 return expandBranchImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2011 return expandCondBranches(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2013 return expandDiv(Inst, IDLoc, Out, STI, false, true) ? MER_Fail in tryExpandInstruction()
2016 return expandDiv(Inst, IDLoc, Out, STI, true, true) ? MER_Fail in tryExpandInstruction()
2019 return expandDiv(Inst, IDLoc, Out, STI, false, false) ? MER_Fail in tryExpandInstruction()
2022 return expandDiv(Inst, IDLoc, Out, STI, true, false) ? MER_Fail in tryExpandInstruction()
2025 return expandTrunc(Inst, false, false, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2028 return expandTrunc(Inst, true, false, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2031 return expandTrunc(Inst, true, true, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2034 return expandUlh(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2036 return expandUlh(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2038 return expandUlw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2040 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2050 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2062 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2068 return expandRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2071 return expandRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2074 return expandDRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2077 return expandDRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2079 return expandAbs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2083 bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, in expandJalWithRegs() argument
2090 JalrInst.setLoc(IDLoc); in expandJalWithRegs()
2123 TOut.emitEmptyDelaySlot(hasShortDelaySlot(JalrInst.getOpcode()), IDLoc, in expandJalWithRegs()
2148 bool IsAddress, SMLoc IDLoc, MCStreamer &Out, in loadImmediate() argument
2153 Error(IDLoc, "instruction requires a 64-bit architecture"); in loadImmediate()
2164 Error(IDLoc, "instruction requires a 32-bit immediate"); in loadImmediate()
2181 unsigned ATReg = getATReg(IDLoc); in loadImmediate()
2195 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2199 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2206 TmpReg = getATReg(IDLoc); in loadImmediate()
2211 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2213 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2218 warnIfNoMacro(IDLoc); in loadImmediate()
2227 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate()
2228 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate()
2230 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2236 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); in loadImmediate()
2237 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in loadImmediate()
2239 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI); in loadImmediate()
2241 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2245 TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI); in loadImmediate()
2247 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI); in loadImmediate()
2249 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2255 Error(IDLoc, "instruction requires a 32-bit immediate"); in loadImmediate()
2265 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); in loadImmediate()
2266 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI); in loadImmediate()
2269 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2274 warnIfNoMacro(IDLoc); in loadImmediate()
2282 IDLoc, Out, STI)) in loadImmediate()
2292 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI); in loadImmediate()
2293 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI); in loadImmediate()
2303 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI); in loadImmediate()
2306 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2311 bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, in expandLoadImm() argument
2319 Is32BitImm, false, IDLoc, Out, STI)) in expandLoadImm()
2327 bool Is32BitAddress, SMLoc IDLoc, in expandLoadAddress() argument
2335 Error(IDLoc, "la used to load 64-bit address"); in expandLoadAddress()
2342 Error(IDLoc, "instruction requires a 64-bit architecture"); in expandLoadAddress()
2348 Is32BitAddress, IDLoc, Out, STI); in expandLoadAddress()
2356 IDLoc, Out, STI); in expandLoadAddress()
2361 bool Is32BitSym, SMLoc IDLoc, in loadAndAddSymbolAddress() argument
2366 warnIfNoMacro(IDLoc); in loadAndAddSymbolAddress()
2371 Error(IDLoc, "expected relocatable expression"); in loadAndAddSymbolAddress()
2375 Error(IDLoc, "expected relocatable expression with only one symbol"); in loadAndAddSymbolAddress()
2388 MCOperand::createExpr(CallExpr), IDLoc, STI); in loadAndAddSymbolAddress()
2421 unsigned ATReg = getATReg(IDLoc); in loadAndAddSymbolAddress()
2428 MCOperand::createExpr(GotExpr), IDLoc, STI); in loadAndAddSymbolAddress()
2432 IDLoc, STI); in loadAndAddSymbolAddress()
2435 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
2449 unsigned ATReg = getATReg(IDLoc); in loadAndAddSymbolAddress()
2469 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
2472 MCOperand::createExpr(HigherExpr), IDLoc, STI); in loadAndAddSymbolAddress()
2473 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
2475 IDLoc, STI); in loadAndAddSymbolAddress()
2476 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
2478 IDLoc, STI); in loadAndAddSymbolAddress()
2479 TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
2492 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
2494 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in loadAndAddSymbolAddress()
2496 MCOperand::createExpr(HigherExpr), IDLoc, STI); in loadAndAddSymbolAddress()
2498 IDLoc, STI); in loadAndAddSymbolAddress()
2499 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI); in loadAndAddSymbolAddress()
2500 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI); in loadAndAddSymbolAddress()
2502 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
2521 unsigned ATReg = getATReg(IDLoc); in loadAndAddSymbolAddress()
2527 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in loadAndAddSymbolAddress()
2529 IDLoc, STI); in loadAndAddSymbolAddress()
2532 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
2540 bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, in expandUncondBranchMMPseudo() argument
2564 Error(IDLoc, "branch target out of range"); in expandUncondBranchMMPseudo()
2566 Error(IDLoc, "branch to misaligned address"); in expandUncondBranchMMPseudo()
2580 TOut.emitEmptyDelaySlot(true, IDLoc, STI); in expandUncondBranchMMPseudo()
2585 bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandBranchImm() argument
2613 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc, in expandBranchImm()
2616 warnIfNoMacro(IDLoc); in expandBranchImm()
2618 unsigned ATReg = getATReg(IDLoc); in expandBranchImm()
2623 IDLoc, Out, STI)) in expandBranchImm()
2626 TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI); in expandBranchImm()
2631 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandMemInst() argument
2635 expandLoadInst(Inst, IDLoc, Out, STI, IsImmOpnd); in expandMemInst()
2638 expandStoreInst(Inst, IDLoc, Out, STI, IsImmOpnd); in expandMemInst()
2641 void MipsAsmParser::expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandLoadInst() argument
2659 Inst.getOperand(2).getImm(), DstReg, IDLoc, in expandLoadInst()
2666 unsigned ATReg = getATReg(IDLoc); in expandLoadInst()
2671 Inst.getOperand(2).getImm(), ATReg, IDLoc, STI); in expandLoadInst()
2684 LoOperand, DstReg, IDLoc, STI); in expandLoadInst()
2690 unsigned ATReg = getATReg(IDLoc); in expandLoadInst()
2695 LoOperand, ATReg, IDLoc, STI); in expandLoadInst()
2698 void MipsAsmParser::expandStoreInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandStoreInst() argument
2709 [&]() { return getATReg(IDLoc); }, IDLoc, STI); in expandStoreInst()
2713 unsigned ATReg = getATReg(IDLoc); in expandStoreInst()
2723 LoOperand, ATReg, IDLoc, STI); in expandStoreInst()
2726 bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, in expandLoadStoreMultiple() argument
2755 bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, in expandCondBranches() argument
2772 warnIfNoMacro(IDLoc); in expandCondBranches()
2775 TrgReg = getATReg(IDLoc); in expandCondBranches()
2833 false, IDLoc, Out, STI)) in expandCondBranches()
2894 IDLoc, STI); in expandCondBranches()
2899 IDLoc, STI); in expandCondBranches()
2900 Warning(IDLoc, "branch is always taken"); in expandCondBranches()
2905 IDLoc, STI); in expandCondBranches()
2906 Warning(IDLoc, "branch is always taken"); in expandCondBranches()
2911 IDLoc, STI); in expandCondBranches()
2916 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
2923 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
2924 Warning(IDLoc, "branch is always taken"); in expandCondBranches()
2948 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
2949 Warning(IDLoc, "branch is always taken"); in expandCondBranches()
2967 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
2975 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
2981 unsigned ATRegNum = getATReg(IDLoc); in expandCondBranches()
2986 warnIfNoMacro(IDLoc); in expandCondBranches()
3005 ReverseOrderSLT ? SrcReg : TrgReg, IDLoc, STI); in expandCondBranches()
3009 ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc, in expandCondBranches()
3014 bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandDiv() argument
3019 warnIfNoMacro(IDLoc); in expandDiv()
3047 Warning(IDLoc, "dividing zero by zero"); in expandDiv()
3051 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDiv()
3055 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDiv()
3059 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI); in expandDiv()
3065 Warning(IDLoc, "division by zero"); in expandDiv()
3068 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDiv()
3072 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDiv()
3084 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDiv()
3089 TOut.emitRRI(Mips::BNE, RtReg, ZeroReg, BranchTargetNoTraps, IDLoc, STI); in expandDiv()
3092 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI); in expandDiv()
3095 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDiv()
3098 TOut.emitR(Mips::MFLO, RdReg, IDLoc, STI); in expandDiv()
3102 unsigned ATReg = getATReg(IDLoc); in expandDiv()
3106 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); in expandDiv()
3109 TOut.emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, STI); in expandDiv()
3110 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI); in expandDiv()
3111 TOut.emitRRI(Mips::DSLL32, ATReg, ATReg, 0x1f, IDLoc, STI); in expandDiv()
3114 TOut.emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, STI); in expandDiv()
3115 TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI); in expandDiv()
3119 TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI); in expandDiv()
3122 TOut.emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, STI); in expandDiv()
3123 TOut.emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, STI); in expandDiv()
3124 TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI); in expandDiv()
3126 TOut.emitR(Mips::MFLO, RdReg, IDLoc, STI); in expandDiv()
3131 SMLoc IDLoc, MCStreamer &Out, in expandTrunc() argument
3144 unsigned ATReg = getATReg(IDLoc); in expandTrunc()
3147 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
3148 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
3149 TOut.emitNop(IDLoc, STI); in expandTrunc()
3150 TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI); in expandTrunc()
3151 TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI); in expandTrunc()
3152 TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI); in expandTrunc()
3153 TOut.emitNop(IDLoc, STI); in expandTrunc()
3156 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
3157 TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI); in expandTrunc()
3158 TOut.emitNop(IDLoc, STI); in expandTrunc()
3164 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
3169 bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, in expandUlh() argument
3174 Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); in expandUlh()
3178 warnIfNoMacro(IDLoc); in expandUlh()
3195 unsigned ATReg = getATReg(IDLoc); in expandUlh()
3207 true, IDLoc, Out, STI)) in expandUlh()
3236 FirstLbuOffset, IDLoc, STI); in expandUlh()
3238 TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondLbuOffset, IDLoc, in expandUlh()
3241 TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI); in expandUlh()
3243 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUlh()
3248 bool MipsAsmParser::expandUlw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandUlw() argument
3253 Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); in expandUlw()
3275 ATReg = getATReg(IDLoc); in expandUlw()
3280 warnIfNoMacro(IDLoc); in expandUlw()
3283 true, IDLoc, Out, STI)) in expandUlw()
3306 TOut.emitRRI(Mips::LWL, DstRegOp.getReg(), FinalSrcReg, LeftLoadOffset, IDLoc, in expandUlw()
3310 IDLoc, STI); in expandUlw()
3315 bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, in expandAliasImmediate() argument
3374 TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI); in expandAliasImmediate()
3376 TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI); in expandAliasImmediate()
3382 bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandRotation() argument
3446 bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc, in expandRotationImm() argument
3511 bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandDRotation() argument
3575 bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc, in expandDRotationImm() argument
3672 bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandAbs() argument
3678 TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI); in expandAbs()
3680 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI); in expandAbs()
3682 TOut.emitEmptyDelaySlot(false, IDLoc, STI); in expandAbs()
3683 TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI); in expandAbs()
3755 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, in MatchAndEmitInstruction() argument
3767 if (processInstruction(Inst, IDLoc, Out, STI)) in MatchAndEmitInstruction()
3772 Error(IDLoc, "instruction requires a CPU feature not currently enabled"); in MatchAndEmitInstruction()
3775 SMLoc ErrorLoc = IDLoc; in MatchAndEmitInstruction()
3778 return Error(IDLoc, "too few operands for instruction"); in MatchAndEmitInstruction()
3782 ErrorLoc = IDLoc; in MatchAndEmitInstruction()
3788 return Error(IDLoc, "invalid instruction"); in MatchAndEmitInstruction()
3790 return Error(IDLoc, "source and destination must be different"); in MatchAndEmitInstruction()
3792 return Error(IDLoc, "registers must be different"); in MatchAndEmitInstruction()
3794 return Error(IDLoc, "invalid operand ($zero) for instruction"); in MatchAndEmitInstruction()
3796 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'"); in MatchAndEmitInstruction()
3798 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3801 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3804 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3807 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3810 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3813 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3816 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3819 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3822 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3825 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3828 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3833 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3836 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3839 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3842 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3845 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3848 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3851 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3854 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3857 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3860 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3863 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3866 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3869 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3873 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3877 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3880 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3883 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3887 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3890 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3893 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3896 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3899 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3902 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3905 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3908 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
3911 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()