626     struct RegIdxOp RegIdx;  member
640     Op->RegIdx.Index = Index;  in CreateReg()
641     Op->RegIdx.RegInfo = RegInfo;  in CreateReg()
642     Op->RegIdx.Kind = RegKind;  in CreateReg()
652     assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");  in getGPR32Reg()
653     AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc);  in getGPR32Reg()
655     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);  in getGPR32Reg()
661     assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");  in getGPRMM16Reg()
663     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);  in getGPRMM16Reg()
669     assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");  in getGPR64Reg()
671     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);  in getGPR64Reg()
678     assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");  in getAFGR64Reg()
679     if (RegIdx.Index % 2 != 0)  in getAFGR64Reg()
681     return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)  in getAFGR64Reg()
682         .getRegister(RegIdx.Index / 2);  in getAFGR64Reg()
688     assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");  in getFGR64Reg()
689     return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)  in getFGR64Reg()
690         .getRegister(RegIdx.Index);  in getFGR64Reg()
696     assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");  in getFGR32Reg()
697     return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)  in getFGR32Reg()
698         .getRegister(RegIdx.Index);  in getFGR32Reg()
704     assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");  in getFGRH32Reg()
705     return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID)  in getFGRH32Reg()
706         .getRegister(RegIdx.Index);  in getFGRH32Reg()
712     assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");  in getFCCReg()
713     return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)  in getFCCReg()
714         .getRegister(RegIdx.Index);  in getFCCReg()
720     assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!");  in getMSA128Reg()
724     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);  in getMSA128Reg()
730     assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");  in getMSACtrlReg()
732     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);  in getMSACtrlReg()
738     assert(isRegIdx() && (RegIdx.Kind & RegKind_COP0) && "Invalid access!");  in getCOP0Reg()
740     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);  in getCOP0Reg()
746     assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");  in getCOP2Reg()
748     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);  in getCOP2Reg()
754     assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!");  in getCOP3Reg()
756     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);  in getCOP3Reg()
762     assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");  in getACC64DSPReg()
764     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);  in getACC64DSPReg()
770     assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");  in getHI32DSPReg()
772     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);  in getHI32DSPReg()
778     assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");  in getLO32DSPReg()
780     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);  in getLO32DSPReg()
786     assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!");  in getCCRReg()
788     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);  in getCCRReg()
794     assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!");  in getHWRegsReg()
796     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);  in getHWRegsReg()
859     if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)  in addFGR32AsmRegOperands()
997     assert((RegIdx.Kind & RegKind_GPR) && "Invalid access!");  in addRegPairOperands()
1001       RegIdx.RegInfo->getRegClass(  in addRegPairOperands()
1006       RegIdx.RegInfo->getRegClass(  in addRegPairOperands()
1021     return isGPRAsmReg() && RegIdx.Index == 0;  in isReg()
1170     return Kind == k_RegPair && RegIdx.Index <= 30;  in isRegPair()
1176     if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&  in getReg()
1177         RegIdx.Kind & RegKind_GPR)  in getReg()
1215     return RegIdx.Index;  in getRegPair()
1329     Op->RegIdx.Index = MOP.RegIdx.Index;  in CreateRegPair()
1330     Op->RegIdx.RegInfo = MOP.RegIdx.RegInfo;  in CreateRegPair()
1331     Op->RegIdx.Kind = MOP.RegIdx.Kind;  in CreateRegPair()
1338     return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;  in isGPRAsmReg()
1341     if (!(isRegIdx() && RegIdx.Kind))  in isMM16AsmReg()
1343     return ((RegIdx.Index >= 2 && RegIdx.Index <= 7)  in isMM16AsmReg()
1344             || RegIdx.Index == 16 || RegIdx.Index == 17);  in isMM16AsmReg()
1347     if (!(isRegIdx() && RegIdx.Kind))  in isMM16AsmRegZero()
1349     return (RegIdx.Index == 0 ||  in isMM16AsmRegZero()
1350             (RegIdx.Index >= 2 && RegIdx.Index <= 7) ||  in isMM16AsmRegZero()
1351             RegIdx.Index == 17);  in isMM16AsmRegZero()
1354     if (!(isRegIdx() && RegIdx.Kind))  in isMM16AsmRegMoveP()
1356     return (RegIdx.Index == 0 || (RegIdx.Index >= 2 && RegIdx.Index <= 3) ||  in isMM16AsmRegMoveP()
1357       (RegIdx.Index >= 16 && RegIdx.Index <= 20));  in isMM16AsmRegMoveP()
1361     return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;  in isFGRAsmReg()
1364     return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31;  in isHWRegsAsmReg()
1367     return isRegIdx() && RegIdx.Kind & RegKind_CCR && RegIdx.Index <= 31;  in isCCRAsmReg()
1370     if (!(isRegIdx() && RegIdx.Kind & RegKind_FCC))  in isFCCAsmReg()
1373       return RegIdx.Index == 0;  in isFCCAsmReg()
1374     return RegIdx.Index <= 7;  in isFCCAsmReg()
1377     return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;  in isACCAsmReg()
1380     return isRegIdx() && RegIdx.Kind & RegKind_COP0 && RegIdx.Index <= 31;  in isCOP0AsmReg()
1383     return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;  in isCOP2AsmReg()
1386     return isRegIdx() && RegIdx.Kind & RegKind_COP3 && RegIdx.Index <= 31;  in isCOP3AsmReg()
1389     return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;  in isMSA128AsmReg()
1392     return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;  in isMSACtrlAsmReg()
1431       OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ">";  in print()
1443       OS << "RegPair<" << RegIdx.Index << "," << RegIdx.Index + 1 << ">";  in print()