Lines Matching refs:RO
1096 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
1099 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1101 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1108 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
1112 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
1114 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1130 class LogicNOR<string opstr, RegisterOperand RO>:
1131 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1133 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
1139 RegisterOperand RO, InstrItinClass itin,
1142 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
1144 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
1148 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
1150 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
1152 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
1156 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
1157 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
1164 class LoadMemory<string opstr, DAGOperand RO, DAGOperand MO,
1168 InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
1169 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
1175 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
1177 LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>;
1179 class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
1182 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
1183 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
1188 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
1191 StoreMemory<opstr, RO, MO, OpNode, Itin, Addr>;
1195 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
1197 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
1199 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
1204 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
1206 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1207 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
1249 RegisterOperand RO, bit DelaySlot = 1> :
1250 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
1252 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,
1262 RegisterOperand RO, bit DelaySlot = 1> :
1263 InstSE<(outs), (ins RO:$rs, opnd:$offset),
1265 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,
1275 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
1276 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
1278 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
1282 RegisterOperand RO>:
1283 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
1285 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
1316 class JumpFR<string opstr, RegisterOperand RO,
1318 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR,
1322 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
1335 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
1336 Register RetReg, RegisterOperand ResRO = RO>:
1337 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>,
1340 class JumpLinkReg<string opstr, RegisterOperand RO>:
1341 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1345 RegisterOperand RO, bit DelaySlot = 1> :
1346 InstSE<(outs), (ins RO:$rs, opnd:$offset),
1359 class TailCallReg<RegisterOperand RO, Instruction JRInst,
1360 RegisterOperand ResRO = RO> :
1361 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
1398 class DEI_FT<string opstr, RegisterOperand RO,
1400 InstSE<(outs RO:$rt), (ins),
1417 class TEQ_FT<string opstr, RegisterOperand RO, Operand ImmOp,
1419 InstSE<(outs), (ins RO:$rs, RO:$rt, ImmOp:$code_),
1422 class TEQI_FT<string opstr, RegisterOperand RO,
1424 InstSE<(outs), (ins RO:$rs, simm16:$imm16),
1429 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
1431 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
1465 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
1467 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
1477 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1478 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
1489 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
1490 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
1496 class EffectiveAddress<string opstr, RegisterOperand RO> :
1497 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
1498 [(set RO:$rt, addr:$addr)], II_ADDIU, FrmI,
1506 class CountLeading0<string opstr, RegisterOperand RO,
1508 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1509 [(set RO:$rd, (ctlz RO:$rs))], itin, FrmR, opstr>;
1511 class CountLeading1<string opstr, RegisterOperand RO,
1513 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1514 [(set RO:$rd, (ctlz (not RO:$rs)))], itin, FrmR, opstr>;
1517 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
1519 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
1520 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
1523 class SubwordSwap<string opstr, RegisterOperand RO,
1525 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin,
1531 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
1532 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
1536 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1539 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size),
1541 [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT,
1544 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1546 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size, RO:$src),
1548 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
1563 class LLBase<string opstr, RegisterOperand RO, DAGOperand MO = mem> :
1564 InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
1570 class SCBase<string opstr, RegisterOperand RO> :
1571 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1578 class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD,
1580 InstSE<(outs RO:$rt), (ins RD:$rd, uimm3:$sel),
1583 class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD,
1585 InstSE<(outs RO:$rd), (ins RD:$rt, uimm3:$sel),
1906 class PseudoIndirectBranchBase<RegisterOperand RO> :
1907 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
1923 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
2322 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
2323 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
2328 RegisterOperand RO> :
2329 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
2333 class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
2334 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),