81                                   const DebugLoc &DL, unsigned DestReg,  in copyPhysReg()  argument
86   if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.  in copyPhysReg()
107       BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)  in copyPhysReg()
115     if (Mips::CCRRegClass.contains(DestReg))  in copyPhysReg()
117     else if (Mips::FGR32RegClass.contains(DestReg))  in copyPhysReg()
119     else if (Mips::HI32RegClass.contains(DestReg))  in copyPhysReg()
120       Opc = Mips::MTHI, DestReg = 0;  in copyPhysReg()
121     else if (Mips::LO32RegClass.contains(DestReg))  in copyPhysReg()
122       Opc = Mips::MTLO, DestReg = 0;  in copyPhysReg()
123     else if (Mips::HI32DSPRegClass.contains(DestReg))  in copyPhysReg()
125     else if (Mips::LO32DSPRegClass.contains(DestReg))  in copyPhysReg()
127     else if (Mips::DSPCCRegClass.contains(DestReg)) {  in copyPhysReg()
130         .addReg(DestReg, RegState::ImplicitDefine);  in copyPhysReg()
132     } else if (Mips::MSACtrlRegClass.contains(DestReg)) {  in copyPhysReg()
134           .addReg(DestReg)  in copyPhysReg()
139   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
141   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
143   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
145   else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.  in copyPhysReg()
156     if (Mips::HI64RegClass.contains(DestReg))  in copyPhysReg()
157       Opc = Mips::MTHI64, DestReg = 0;  in copyPhysReg()
158     else if (Mips::LO64RegClass.contains(DestReg))  in copyPhysReg()
159       Opc = Mips::MTLO64, DestReg = 0;  in copyPhysReg()
160     else if (Mips::FGR64RegClass.contains(DestReg))  in copyPhysReg()
163   else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg  in copyPhysReg()
172   if (DestReg)  in copyPhysReg()
173     MIB.addReg(DestReg, RegState::Define);  in copyPhysReg()
253                  unsigned DestReg, int FI, const TargetRegisterClass *RC,  in loadRegFromStack()  argument
262                          (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||  in loadRegFromStack()
263                           DestReg == Mips::HI0 || DestReg == Mips::HI0_64);  in loadRegFromStack()
303     BuildMI(MBB, I, DL, get(Opc), DestReg)  in loadRegFromStack()
312     if (DestReg == Mips::HI0)  in loadRegFromStack()
317       if (DestReg == Mips::HI0_64)  in loadRegFromStack()