Lines Matching refs:regclass
69 multiclass SHFL<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
75 (outs regclass:$dst),
76 (ins regclass:$src, Int32Regs:$offset, Int32Regs:$mask),
78 [(set regclass:$dst, (IntOp regclass:$src, Int32Regs:$offset, Int32Regs:$mask))]>;
81 (outs regclass:$dst),
82 (ins regclass:$src, i32imm:$offset, Int32Regs:$mask),
84 [(set regclass:$dst, (IntOp regclass:$src, imm:$offset, Int32Regs:$mask))]>;
87 (outs regclass:$dst),
88 (ins regclass:$src, Int32Regs:$offset, i32imm:$mask),
90 [(set regclass:$dst, (IntOp regclass:$src, Int32Regs:$offset, imm:$mask))]>;
93 (outs regclass:$dst),
94 (ins regclass:$src, i32imm:$offset, i32imm:$mask),
96 [(set regclass:$dst, (IntOp regclass:$src, imm:$offset, imm:$mask))]>;
881 multiclass F_ATOMIC_2_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
884 def reg : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, regclass:$b),
890 [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b))]>,
892 def imm : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, IMMType:$b),
898 [(set regclass:$dst, (IntOp ptrclass:$addr, IMM:$b))]>,
901 multiclass F_ATOMIC_2<NVPTXRegClass regclass, string SpaceStr, string TypeStr,
903 defm p32 : F_ATOMIC_2_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
905 defm p64 : F_ATOMIC_2_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
910 multiclass F_ATOMIC_2_NEG_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
913 def reg : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, regclass:$b),
928 [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b))]>,
931 multiclass F_ATOMIC_2_NEG<NVPTXRegClass regclass, string SpaceStr,
934 defm p32: F_ATOMIC_2_NEG_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
936 defm p64: F_ATOMIC_2_NEG_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
941 multiclass F_ATOMIC_3_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
944 def reg : NVPTXInst<(outs regclass:$dst),
945 (ins ptrclass:$addr, regclass:$b, regclass:$c),
951 [(set regclass:$dst,
952 (IntOp ptrclass:$addr, regclass:$b, regclass:$c))]>,
954 def imm1 : NVPTXInst<(outs regclass:$dst),
955 (ins ptrclass:$addr, IMMType:$b, regclass:$c),
961 [(set regclass:$dst, (IntOp ptrclass:$addr, imm:$b, regclass:$c))]>,
963 def imm2 : NVPTXInst<(outs regclass:$dst),
964 (ins ptrclass:$addr, regclass:$b, IMMType:$c),
970 [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b, imm:$c))]>,
972 def imm3 : NVPTXInst<(outs regclass:$dst),
979 [(set regclass:$dst, (IntOp ptrclass:$addr, imm:$b, imm:$c))]>,
982 multiclass F_ATOMIC_3<NVPTXRegClass regclass, string SpaceStr, string TypeStr,
984 defm p32 : F_ATOMIC_3_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
986 defm p64 : F_ATOMIC_3_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
1392 multiclass LDU_G<string TyStr, NVPTXRegClass regclass> {
1393 def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1396 def areg64: NVPTXInst<(outs regclass:$result), (ins Int64Regs:$src),
1399 def avar: NVPTXInst<(outs regclass:$result), (ins imemAny:$src),
1402 def ari : NVPTXInst<(outs regclass:$result), (ins MEMri:$src),
1405 def ari64 : NVPTXInst<(outs regclass:$result), (ins MEMri64:$src),
1422 multiclass VLDU_G_ELE_V2<string TyStr, NVPTXRegClass regclass> {
1423 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1426 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1429 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1432 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1435 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1440 multiclass VLDU_G_ELE_V4<string TyStr, NVPTXRegClass regclass> {
1441 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1442 regclass:$dst4), (ins Int32Regs:$src),
1444 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1445 regclass:$dst4), (ins Int64Regs:$src),
1447 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1448 regclass:$dst4), (ins MEMri:$src),
1450 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1451 regclass:$dst4), (ins MEMri64:$src),
1453 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1454 regclass:$dst4), (ins imemAny:$src),
1491 multiclass LDG_G<string TyStr, NVPTXRegClass regclass> {
1492 def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1495 def areg64: NVPTXInst<(outs regclass:$result), (ins Int64Regs:$src),
1498 def avar: NVPTXInst<(outs regclass:$result), (ins imemAny:$src),
1501 def ari : NVPTXInst<(outs regclass:$result), (ins MEMri:$src),
1504 def ari64 : NVPTXInst<(outs regclass:$result), (ins MEMri64:$src),
1529 multiclass VLDG_G_ELE_V2<string TyStr, NVPTXRegClass regclass> {
1530 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1533 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1536 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1539 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1542 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1547 multiclass VLDG_G_ELE_V4<string TyStr, NVPTXRegClass regclass> {
1548 def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1549 regclass:$dst4), (ins Int32Regs:$src),
1551 def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1552 regclass:$dst4), (ins Int64Regs:$src),
1554 def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1555 regclass:$dst4), (ins MEMri:$src),
1557 def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1558 regclass:$dst4), (ins MEMri64:$src),
1560 def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1561 regclass:$dst4), (ins imemAny:$src),