Lines Matching refs:cls2

1269               RegisterOperand cls1, RegisterOperand cls2>
1270   : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
1272            [(set cls1:$R1, (operator cls2:$R2))]> {
1278                RegisterOperand cls1, RegisterOperand cls2>
1279   : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
1281             [(set cls1:$R1, (operator cls2:$R2))]> {
1287                RegisterOperand cls2>
1288   : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2),
1296                 RegisterOperand cls2>
1297   : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2, imm32zx4:$R4),
1303                    RegisterOperand cls2>
1304   : InstRRF<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$valid, cond4:$R3),
1323                       RegisterOperand cls2>
1324   : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, imm32zx4:$R3),
1344                         RegisterOperand cls2, bits<4> ccmask>
1345   : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1523                RegisterOperand cls1, RegisterOperand cls2>
1524   : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1526            [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
1534                 RegisterOperand cls1, RegisterOperand cls2>
1535   : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1537             [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
1545                 RegisterOperand cls1, RegisterOperand cls2>
1546   : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
1548             [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
1555                  RegisterOperand cls1, RegisterOperand cls2>
1556   : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
1558             [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
1564                         RegisterOperand cls2> {
1567       def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
1570       def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
1576                          RegisterOperand cls2> {
1579       def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
1582       def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
1877                 RegisterOperand cls1, RegisterOperand cls2>
1878   : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
1880            [(operator cls1:$R1, cls2:$R2)]> {
1887                  RegisterOperand cls1, RegisterOperand cls2>
1888   : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
1890             [(operator cls1:$R1, cls2:$R2)]> {
2321                        RegisterOperand cls2>
2323              (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2396                     RegisterOperand cls1, RegisterOperand cls2>
2397   : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
2398            [(set cls1:$R1, (operator cls2:$R2))]> {
2460 class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
2462            (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2599 class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2>
2600  : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>;
2647 class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
2649           (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,