Lines Matching refs:CurrState
296 IntelExprState CurrState = State; in onOr() local
308 PrevState = CurrState; in onOr()
311 IntelExprState CurrState = State; in onXor() local
323 PrevState = CurrState; in onXor()
326 IntelExprState CurrState = State; in onAnd() local
338 PrevState = CurrState; in onAnd()
341 IntelExprState CurrState = State; in onLShift() local
353 PrevState = CurrState; in onLShift()
356 IntelExprState CurrState = State; in onRShift() local
368 PrevState = CurrState; in onRShift()
371 IntelExprState CurrState = State; in onPlus() local
381 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) { in onPlus()
394 PrevState = CurrState; in onPlus()
397 IntelExprState CurrState = State; in onMinus() local
414 if (!(CurrState == IES_PLUS || CurrState == IES_MINUS || in onMinus()
415 CurrState == IES_MULTIPLY || CurrState == IES_DIVIDE || in onMinus()
416 CurrState == IES_LPAREN || CurrState == IES_LBRAC)) in onMinus()
418 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) { in onMinus()
431 PrevState = CurrState; in onMinus()
434 IntelExprState CurrState = State; in onNot() local
444 PrevState = CurrState; in onNot()
447 IntelExprState CurrState = State; in onRegister() local
473 PrevState = CurrState; in onRegister()
492 IntelExprState CurrState = State; in onInteger() local
509 if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) { in onInteger()
526 CurrState == IES_MINUS) { in onInteger()
536 CurrState == IES_NOT) { in onInteger()
545 PrevState = CurrState; in onInteger()
588 IntelExprState CurrState = State; in onRBrac() local
597 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) { in onRBrac()
610 PrevState = CurrState; in onRBrac()
613 IntelExprState CurrState = State; in onLParen() local
636 (CurrState == IES_MINUS || CurrState == IES_NOT)) { in onLParen()
644 PrevState = CurrState; in onLParen()