Lines Matching refs:SimpleTy
359 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitLoad()
511 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
660 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
1333 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpOpcode()
1350 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpImmediateOpcode()
1516 if (SrcVT.SimpleTy == MVT::i1) { in X86SelectZExt()
1529 switch (SrcVT.SimpleTy) { in X86SelectZExt()
1646 switch (SourceVT.SimpleTy) { in X86SelectBranch()
1836 switch (VT.SimpleTy) { in X86SelectDivRem()
1880 if (VT.SimpleTy == MVT::i16) { in X86SelectDivRem()
1884 } else if (VT.SimpleTy == MVT::i32) { in X86SelectDivRem()
1888 } else if (VT.SimpleTy == MVT::i64) { in X86SelectDivRem()
2098 switch (RetVT.SimpleTy) { in X86FastEmitSSESelect()
2135 (RetVT.SimpleTy == MVT::f32) ? X86::VCMPSSrr : X86::VCMPSDrr; in X86FastEmitSSESelect()
2137 (RetVT.SimpleTy == MVT::f32) ? X86::VBLENDVPSrr : X86::VBLENDVPDrr; in X86FastEmitSSESelect()
2164 switch (RetVT.SimpleTy) { in X86FastEmitPseudoSelect()
2519 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
2660 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
2762 TII.get(Opc[IsDec][VT.SimpleTy-MVT::i8]), ResultReg) in fastLowerIntrinsicCall()
2789 TII.get(TargetOpcode::COPY), Reg[VT.SimpleTy-MVT::i8]) in fastLowerIntrinsicCall()
2791 ResultReg = fastEmitInst_r(MULOpc[VT.SimpleTy-MVT::i8], in fastLowerIntrinsicCall()
2805 ResultReg = fastEmitInst_rr(MULOpc[VT.SimpleTy-MVT::i8], in fastLowerIntrinsicCall()
2855 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
2929 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
2967 switch (VT.SimpleTy) { in fastLowerArguments()
3145 if (ArgVT.SimpleTy == MVT::i1) in fastLowerCall()
3159 if (ArgVT.SimpleTy == MVT::i1) { in fastLowerCall()
3486 switch (VT.SimpleTy) { in X86MaterializeInt()
3508 switch (VT.SimpleTy) { in X86MaterializeInt()
3547 switch (VT.SimpleTy) { in X86MaterializeFP()
3701 switch (VT.SimpleTy) { in fastMaterializeFloatZero()