alu64.ll - OpenGrok cross reference for /external/llvm/test/CodeGen/Hexagon/alu64.ll

Lines Matching refs:hexagon
1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
7   %0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt)
15   %0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt)
23   %0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt)
31   %0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt)
39   %0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt)
47   %0 = tail call i32 @llvm.hexagon.A4.rcmpeqi(i32 %Rs, i32 23)
55   %0 = tail call i32 @llvm.hexagon.A4.rcmpneqi(i32 %Rs, i32 47)
63   %0 = tail call i32 @llvm.hexagon.A4.cmpbeq(i32 %Rs, i32 %Rt)
71   %0 = tail call i32 @llvm.hexagon.A4.cmpbgt(i32 %Rs, i32 %Rt)
79   %0 = tail call i32 @llvm.hexagon.A4.cmpbgtu(i32 %Rs, i32 %Rt)
87   %0 = tail call i32 @llvm.hexagon.A4.cmpbeqi(i32 %Rs, i32 56)
95   %0 = tail call i32 @llvm.hexagon.A4.cmpbgti(i32 %Rs, i32 29)
103   %0 = tail call i32 @llvm.hexagon.A4.cmpbgtui(i32 %Rs, i32 111)
111   %0 = tail call i32 @llvm.hexagon.A4.cmpheq(i32 %Rs, i32 %Rt)
119   %0 = tail call i32 @llvm.hexagon.A4.cmphgt(i32 %Rs, i32 %Rt)
127   %0 = tail call i32 @llvm.hexagon.A4.cmphgtu(i32 %Rs, i32 %Rt)
135   %0 = tail call i32 @llvm.hexagon.A4.cmpheqi(i32 %Rs, i32 -123)
143   %0 = tail call i32 @llvm.hexagon.A4.cmphgti(i32 %Rs, i32 -3)
151   %0 = tail call i32 @llvm.hexagon.A4.cmphgtui(i32 %Rs, i32 13)
159   %0 = tail call i64 @llvm.hexagon.C2.vmux(i32 %Pu, i64 %Rs, i64 %Rt)
167   %0 = tail call i32 @llvm.hexagon.A4.vcmpbeq.any(i64 %Rs, i64 %Rt)
175   %0 = tail call i64 @llvm.hexagon.A2.addp(i64 %Rs, i64 %Rt)
183   %0 = tail call i64 @llvm.hexagon.A2.addpsat(i64 %Rs, i64 %Rt)
191   %0 = tail call i64 @llvm.hexagon.A2.subp(i64 %Rs, i64 %Rt)
199   %0 = tail call i64 @llvm.hexagon.A2.addsp(i32 %Rs, i64 %Rt)
207   %0 = tail call i64 @llvm.hexagon.A2.andp(i64 %Rs, i64 %Rt)
215   %0 = tail call i64 @llvm.hexagon.A2.orp(i64 %Rs, i64 %Rt)
223   %0 = tail call i64 @llvm.hexagon.A2.xorp(i64 %Rs, i64 %Rt)
231   %0 = tail call i64 @llvm.hexagon.A4.andnp(i64 %Rs, i64 %Rt)
239   %0 = tail call i64 @llvm.hexagon.A4.ornp(i64 %Rs, i64 %Rt)
247   %0 = tail call i32 @llvm.hexagon.A2.addh.l16.ll(i32 %Rs, i32 %Rt)
255   %0 = tail call i32 @llvm.hexagon.A2.addh.l16.hl(i32 %Rs, i32 %Rt)
263   %0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %Rs, i32 %Rt)
271   %0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32 %Rs, i32 %Rt)
279   %0 = tail call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %Rs, i32 %Rt)
287   %0 = tail call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %Rs, i32 %Rt)
295   %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %Rs, i32 %Rt)
303   %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %Rs, i32 %Rt)
311   %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %Rs, i32 %Rt)
319   %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %Rs, i32 %Rt)
327   %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32 %Rs, i32 %Rt)
335   %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32 %Rs, i32 %Rt)
343   %0 = tail call i32 @llvm.hexagon.A2.subh.l16.ll(i32 %Rs, i32 %Rt)
351   %0 = tail call i32 @llvm.hexagon.A2.subh.l16.hl(i32 %Rs, i32 %Rt)
359   %0 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %Rs, i32 %Rt)
367   %0 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32 %Rs, i32 %Rt)
375   %0 = tail call i32 @llvm.hexagon.A2.subh.h16.ll(i32 %Rs, i32 %Rt)
383   %0 = tail call i32 @llvm.hexagon.A2.subh.h16.lh(i32 %Rs, i32 %Rt)
391   %0 = tail call i32 @llvm.hexagon.A2.subh.h16.hl(i32 %Rs, i32 %Rt)
399   %0 = tail call i32 @llvm.hexagon.A2.subh.h16.hh(i32 %Rs, i32 %Rt)
407   %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32 %Rs, i32 %Rt)
415   %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32 %Rs, i32 %Rt)
423   %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32 %Rs, i32 %Rt)
431   %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32 %Rs, i32 %Rt)
439   %0 = tail call i32 @llvm.hexagon.S4.andi.asl.ri(i32 1, i32 %Rs, i32 2)
447   %0 = tail call i32 @llvm.hexagon.S4.ori.asl.ri(i32 1, i32 %Rs, i32 2)
455   %0 = tail call i32 @llvm.hexagon.S4.addi.asl.ri(i32 1, i32 %Rs, i32 2)
463   %0 = tail call i32 @llvm.hexagon.S4.subi.asl.ri(i32 1, i32 %Rs, i32 2)
471   %0 = tail call i32 @llvm.hexagon.S4.andi.lsr.ri(i32 1, i32 %Rs, i32 2)
479   %0 = tail call i32 @llvm.hexagon.S4.ori.lsr.ri(i32 1, i32 %Rs, i32 2)
487   %0 = tail call i32 @llvm.hexagon.S4.addi.lsr.ri(i32 1, i32 %Rs, i32 2)
495   %0 = tail call i32 @llvm.hexagon.S4.subi.lsr.ri(i32 1, i32 %Rs, i32 2)
503   %0 = tail call i64 @llvm.hexagon.A4.bitsplit(i32 %Rs, i32 %Rt)
511   %0 = tail call i32 @llvm.hexagon.A4.modwrapu(i32 %Rs, i32 %Rt)
519   %0 = tail call i32 @llvm.hexagon.S2.parityp(i64 %Rs, i64 %Rt)
527   %0 = tail call i32 @llvm.hexagon.S4.parity(i32 %Rs, i32 %Rt)
531 declare i32 @llvm.hexagon.C2.cmpeqp(i64, i64) #1
532 declare i32 @llvm.hexagon.C2.cmpgtp(i64, i64) #1
533 declare i32 @llvm.hexagon.C2.cmpgtup(i64, i64) #1
534 declare i32 @llvm.hexagon.A4.rcmpeq(i32, i32) #1
535 declare i32 @llvm.hexagon.A4.rcmpneq(i32, i32) #1
536 declare i32 @llvm.hexagon.A4.rcmpeqi(i32, i32) #1
537 declare i32 @llvm.hexagon.A4.rcmpneqi(i32, i32) #1
538 declare i32 @llvm.hexagon.A4.cmpbeq(i32, i32) #1
539 declare i32 @llvm.hexagon.A4.cmpbgt(i32, i32) #1
540 declare i32 @llvm.hexagon.A4.cmpbgtu(i32, i32) #1
541 declare i32 @llvm.hexagon.A4.cmpbeqi(i32, i32) #1
542 declare i32 @llvm.hexagon.A4.cmpbgti(i32, i32) #1
543 declare i32 @llvm.hexagon.A4.cmpbgtui(i32, i32) #1
544 declare i32 @llvm.hexagon.A4.cmpheq(i32, i32) #1
545 declare i32 @llvm.hexagon.A4.cmphgt(i32, i32) #1
546 declare i32 @llvm.hexagon.A4.cmphgtu(i32, i32) #1
547 declare i32 @llvm.hexagon.A4.cmpheqi(i32, i32) #1
548 declare i32 @llvm.hexagon.A4.cmphgti(i32, i32) #1
549 declare i32 @llvm.hexagon.A4.cmphgtui(i32, i32) #1
550 declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64) #1
551 declare i32 @llvm.hexagon.A4.vcmpbeq.any(i64, i64) #1
552 declare i64 @llvm.hexagon.A2.addp(i64, i64) #1
553 declare i64 @llvm.hexagon.A2.addpsat(i64, i64) #1
554 declare i64 @llvm.hexagon.A2.subp(i64, i64) #1
555 declare i64 @llvm.hexagon.A2.addsp(i32, i64) #1
556 declare i64 @llvm.hexagon.A2.andp(i64, i64) #1
557 declare i64 @llvm.hexagon.A2.orp(i64, i64) #1
558 declare i64 @llvm.hexagon.A2.xorp(i64, i64) #1
559 declare i64 @llvm.hexagon.A4.ornp(i64, i64) #1
560 declare i64 @llvm.hexagon.A4.andnp(i64, i64) #1
561 declare i32 @llvm.hexagon.A2.addh.l16.ll(i32, i32) #1
562 declare i32 @llvm.hexagon.A2.addh.l16.hl(i32, i32) #1
563 declare i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32, i32) #1
564 declare i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32, i32) #1
565 declare i32 @llvm.hexagon.A2.addh.h16.ll(i32, i32) #1
566 declare i32 @llvm.hexagon.A2.addh.h16.lh(i32, i32) #1
567 declare i32 @llvm.hexagon.A2.addh.h16.hl(i32, i32) #1
568 declare i32 @llvm.hexagon.A2.addh.h16.hh(i32, i32) #1
569 declare i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32, i32) #1
570 declare i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32, i32) #1
571 declare i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32, i32) #1
572 declare i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32, i32) #1
573 declare i32 @llvm.hexagon.A2.subh.l16.ll(i32, i32) #1
574 declare i32 @llvm.hexagon.A2.subh.l16.hl(i32, i32) #1
575 declare i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32, i32) #1
576 declare i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32, i32) #1
577 declare i32 @llvm.hexagon.A2.subh.h16.ll(i32, i32) #1
578 declare i32 @llvm.hexagon.A2.subh.h16.lh(i32, i32) #1
579 declare i32 @llvm.hexagon.A2.subh.h16.hl(i32, i32) #1
580 declare i32 @llvm.hexagon.A2.subh.h16.hh(i32, i32) #1
581 declare i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32, i32) #1
582 declare i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32, i32) #1
583 declare i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32, i32) #1
584 declare i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32, i32) #1
585 declare i64 @llvm.hexagon.A4.bitsplit(i32, i32) #1
586 declare i32 @llvm.hexagon.A4.modwrapu(i32, i32) #1
587 declare i32 @llvm.hexagon.S2.parityp(i64, i64) #1
588 declare i32 @llvm.hexagon.S4.parity(i32, i32) #1
589 declare i32 @llvm.hexagon.S4.andi.asl.ri(i32, i32, i32) #1
590 declare i32 @llvm.hexagon.S4.ori.asl.ri(i32, i32, i32) #1
591 declare i32 @llvm.hexagon.S4.addi.asl.ri(i32, i32, i32) #1
592 declare i32 @llvm.hexagon.S4.subi.asl.ri(i32, i32, i32) #1
593 declare i32 @llvm.hexagon.S4.andi.lsr.ri(i32, i32, i32) #1
594 declare i32 @llvm.hexagon.S4.ori.lsr.ri(i32, i32, i32) #1
595 declare i32 @llvm.hexagon.S4.addi.lsr.ri(i32, i32, i32) #1
596 declare i32 @llvm.hexagon.S4.subi.lsr.ri(i32, i32, i32) #1