Lines Matching refs:R6

3 ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=ALL,32R6
7 ; RUN: llc -march=mips -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s -check-prefixes=ALL,64R6
26 ; 32R6-DAG:      mul  $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
27 ; 32R6-DAG:      addu $[[T1:[0-9]+]], $[[T0]], $6
28 ; 32R6-DAG:      sltu $[[T2:[0-9]+]], $[[T1]], $6
29 ; 32R6-DAG:      sra  $[[T3:[0-9]+]], $6, 31
30 ; 32R6-DAG:      addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
31 ; 32R6-DAG:      muh  $[[T5:[0-9]+]], ${{[45]}}, ${{[45]}}
32 ; 32R6-DAG:      addu $2, $[[T5]], $[[T4]]
41 ; 64R6-DAG:      sll $[[T0:[0-9]+]], $4, 0
42 ; 64R6-DAG:      sll $[[T1:[0-9]+]], $5, 0
43 ; 64R6-DAG:      dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
44 ; 64R6-DAG:      sll $[[T3:[0-9]+]], $6, 0
45 ; 64R6-DAG:      daddu $2, $[[T2]], $[[T3]]
72 ; 32R6-DAG:      mul  $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
73 ; 32R6-DAG:      addu $[[T1:[0-9]+]], $[[T0]], $6
74 ; 32R6-DAG:      sltu $[[T2:[0-9]+]], $[[T1]], $6
76 ; 32R6-DAG:      muhu $[[T3:[0-9]+]], ${{[45]}}, ${{[45]}}
77 ; 32R6-DAG:      addu $2, $[[T3]], $[[T2]]
83 ; 64R6-DAG:      dmul $[[T0:[0-9]+]], $5, $4
84 ; 64R6-DAG:      daddu $2, $[[T0]], $6
110 ; 32R6-DAG:      mul  $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
111 ; 32R6-DAG:      addu $[[T1:[0-9]+]], $[[T0]], $7
112 ; 32R6-DAG:      sltu $[[T2:[0-9]+]], $[[T1]], $7
113 ; 32R6-DAG:      addu $[[T4:[0-9]+]], $[[T2]], $6
114 ; 32R6-DAG:      muh  $[[T5:[0-9]+]], ${{[45]}}, ${{[45]}}
115 ; 32R6-DAG:      addu $2, $[[T5]], $[[T4]]
123 ; 64R6-DAG:      sll $[[T0:[0-9]+]], $4, 0
124 ; 64R6-DAG:      sll $[[T1:[0-9]+]], $5, 0
125 ; 64R6-DAG:      dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
126 ; 64R6-DAG:      daddu $2, $[[T2]], $6
151 ; 32R6-DAG:      muh  $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
152 ; 32R6-DAG:      mul  $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
153 ; 32R6-DAG:      sltu $[[T3:[0-9]+]], $6, $[[T1]]
154 ; 32R6-DAG:      addu $[[T4:[0-9]+]], $[[T3]], $[[T0]]
155 ; 32R6-DAG:      sra  $[[T5:[0-9]+]], $6, 31
156 ; 32R6-DAG:      subu $2, $[[T5]], $[[T4]]
157 ; 32R6-DAG:      subu $3, $6, $[[T1]]
166 ; 64R6-DAG:      sll $[[T0:[0-9]+]], $4, 0
167 ; 64R6-DAG:      sll $[[T1:[0-9]+]], $5, 0
168 ; 64R6-DAG:      dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
169 ; 64R6-DAG:      sll $[[T3:[0-9]+]], $6, 0
170 ; 64R6-DAG:      dsubu $2, $[[T3]], $[[T2]]
197 ; 32R6-DAG:      muhu $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
198 ; 32R6-DAG:      mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
200 ; 32R6-DAG:      sltu $[[T2:[0-9]+]], $6, $[[T1]]
201 ; 32R6-DAG:      addu $[[T3:[0-9]+]], $[[T2]], $[[T0]]
202 ; 32R6-DAG:      negu $2, $[[T3]]
203 ; 32R6-DAG:      subu $3, $6, $[[T1]]
209 ; 64R6-DAG:      dmul $[[T0:[0-9]+]], $5, $4
210 ; 64R6-DAG:      dsubu $2, $6, $[[T0]]
237 ; 32R6-DAG:      muh $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}}
238 ; 32R6-DAG:      mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}}
239 ; 32R6-DAG:      sltu $[[T2:[0-9]+]], $7, $[[T1]]
240 ; 32R6-DAG:      addu $[[T3:[0-9]+]], $[[T2]], $[[T0]]
241 ; 32R6-DAG:      subu $2, $6, $[[T3]]
242 ; 32R6-DAG:      subu $3, $7, $[[T1]]
250 ; 64R6-DAG:      sll $[[T0:[0-9]+]], $4, 0
251 ; 64R6-DAG:      sll $[[T1:[0-9]+]], $5, 0
252 ; 64R6-DAG:      dmul $[[T2:[0-9]+]], $[[T1]], $[[T0]]
253 ; 64R6-DAG:      dsubu $2, $6, $[[T2]]