Lines Matching refs:sdc1
13 ; Check that -mno-ldc1-sdc1 disables [sl]dc1
14 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
17 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
20 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
23 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
26 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \
31 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
34 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
37 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
40 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
43 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \
48 ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \
51 ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \
54 ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \
202 ; 32R1-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
204 ; 32R2-LDXC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
206 ; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
212 ; MM: sdc1 $f12, 0($[[R3]])
226 ; MM-STATIC-PIC: sdc1 $f12, %lo(g0)($[[R0]])
305 ; 32R1-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
310 ; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
314 ; MM: sdc1 $f12, 0($[[R1]])
327 ; MM-STATIC-PIC: sdc1 $f12, 0($[[R1]])